TE28F008xxx Intel Corporation, TE28F008xxx Datasheet - Page 15

• Manufacturer Part Number: TE28F008xxx
• Description: (TE28F Series) 3 Volt Advanced Boot Block Flash Memory
• Manufacturer: Intel Corporation

3.1.5
3.2
3.2.1
3UHOLPLQDU\
If RP# is taken low for time t
aborted and the memory contents at the aborted location (for a program) or block (for an erase) are
no longer valid, since the data may be partially erased or written. The abort process goes through
the following sequence: When RP# goes low, the device shuts down the operation in progress, a
process which takes time t
array mode (if RP# has gone high during t
low after t
time t
discussed in the previous paragraph. However, in this case, these delays are referenced to the end
of t
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, processor expects to read from the flash memory. Automated flash memories
provide status information when read during program or block erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU initialization may not occur because the flash
memory may be providing status information instead of array data. Intel
proper CPU initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
Write
A write takes place when both CE# and WE# are low and OE# is high. Commands are written to
the Command User Interface (CUI) using standard microprocessor write timings to control flash
operations. The CUI does not occupy an addressable memory location. The address and data buses
are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first.
illustrates a program and erase operation. The available commands are shown in
Appendix A
using CUI commands.
There are two commands that modify array data: Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User Interface (CUI) initiates a sequence of internally-
timed functions that culminate in the completion of the requested task (unless that operation is
aborted by either RP# being driven to V
Modes of Operation
The flash memory has four read modes and two write modes. The read modes are read array, read
identifier, read status and read query (see
erase. Three additional modes (erase suspend to program, erase suspend to read and program
suspend to read) are available only during suspended operations. These modes are reached using
the commands summarized in
Appendix
Read Array
When RP# transitions from V
respond to the read control inputs (CE#, address inputs, and OE#) without any additional CUI
commands.
PLRH
PHQV
rather than when RP# goes high.
PLRH
A.
or t
provides detailed information on moving between the different modes of operation
PHWL
,
Figure
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
/t
PHEL
9C). In both cases, after returning from an aborted operation, the relevant
PLRH
must be waited before a read or write operation is initiated, as
PLPH
IL
Table
to complete. After this time t
(reset) to V
during a program or erase operation, the operation will be
4. A comprehensive chart showing the state transitions is in
IL
PLRH
Appendix
for t
IH
, the device defaults to read array mode and will
,
PLRH
Figure
B). The write modes are program and block
or an appropriate suspend command).
9B) or enter reset mode (if RP# is still logic
PLRH
, the part will either reset to read
®
Flash memories allow
Table
6, and
Figure 8
9