24LC21A-IP MicrochipTechnology, 24LC21A-IP Datasheet - Page 9

• Manufacturer Part Number: 24LC21A-IP
• Description: 1K2.5VDualModeI2CSerialEEPROM
• Manufacturer: MicrochipTechnology

4.0
4.1
Following the start signal from the master, the slave
address (four bits), three zero bits (000) and the R/W bit
which is a logic low are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24LC21A. After receiving
another acknowledge signal from the 24LC21A the
master device will transmit the data word to be written
into the addressed memory location. The 24LC21A
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24LC21A will not generate acknowl-
edge signals (Figure 4-1).
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high to low during the self-timed
program operation will not halt programming of the
device.
FIGURE 4-1:
FIGURE 4-2:
1996 Microchip Technology Inc.
WRITE OPERATION
Byte Write
SCL
SDA
VCLK
IN
BUS ACTIVITY
SDA LINE
BUS ACTIVITY
VCLK
BYTE WRITE
VCLK WRITE ENABLE TIMING
MASTER
T
VHST
S
T
A
R
T
S
CONTROL
BYTE
T
HD
:
STA
Preliminary
C
A
K
ADDRESS
4.2
The write control byte, word address and the first data
byte are transmitted to the 24LC21A in the same way
as in a byte write. But instead of generating a stop
condition the master transmits up to eight data bytes to
the 24LC21A which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an
internal write cycle will begin (Figure 4-3).
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high to low during the self-timed
program operation will not halt programming of the
device.
WORD
T
HD
:
STO
Page Write
C
A
K
DATA
T
SPVL
24LC21A
A
C
K
O
S
P
T
P
DS21160B-page 9