24LC21A-IP MicrochipTechnology, 24LC21A-IP Datasheet - Page 3

• Manufacturer Part Number: 24LC21A-IP
• Description: 1K2.5VDualModeI2CSerialEEPROM
• Manufacturer: MicrochipTechnology

TABLE 1-3:
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time T
START condition setup
time
Data input hold time
Data input setup time
STOP condition setup time T
Output valid from clock
Bus free time
Output fall time from V
minimum to V
Input filter spike suppres-
sion (SDA and SCL pins)
Write cycle time
Transmit-Only Mode Parameters
Output valid from VCLK
VCLK high time
VCLK low time
VCLK setup time
VCLK hold time
Mode transition time
Transmit-Only power up
time
Input filter spike suppres-
sion (VCLK pin)
Endurance
Note 1: Not 100% tested. C
1996 Microchip Technology Inc.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-
3: The combined T
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
Parameter
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
suppression. This eliminates the need for a T
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
IL
maximum
AC CHARACTERISTICS
IH
SP
and V
T
B
Symbol
T
T
T
T
T
T
T
T
HD
HD
SU
SU
SU
T
F
T
T
T
T
= Total capacitance of one bus line in pF.
T
VHIGH
T
T
VLOW
T
VHST
SPVL
HIGH
LOW
T
T
VPU
—
CLK
BUF
VAA
VHZ
SPV
WR
AA
OF
SP
:
:
:
:
:
R
F
STO
STA
STA
DAT
DAT
HYS
specifications are due to Schmitt trigger inputs which provide noise and spike
Standard Mode
Vcc= 2.5-5.5V
4000
4700
4000
4700
4000
4700
4000
4700
4000
10M
Min
250
—
—
—
—
—
—
—
—
—
—
0
0
0
Preliminary
1000
3500
2000
1000
Max
100
300
250
100
50
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
specification for standard operation.
Vcc= 4.5 - 5.5V
0.1 C
1300
1300
1300
20 +
10M
Min
600
600
600
100
600
600
600
Fast Mode
—
—
—
—
—
—
—
—
—
0
0
0
B
1000
Max
400
300
300
900
250
500
100
50
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
cycles
Units
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
(Note 2)
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
(Note 3)
Byte or Page mode
25 C, Vcc = 5.0V, Block Mode
(Note 4)
24LC21A
Remarks
B
DS21160B-page 3
100 pF