24LC21A-IP MicrochipTechnology, 24LC21A-IP Datasheet - Page 7

• Manufacturer Part Number: 24LC21A-IP
• Description: 1K2.5VDualModeI2CSerialEEPROM
• Manufacturer: MicrochipTechnology

3.1
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (Figure 3-4).
3.1.1
Both data and clock lines remain HIGH.
3.1.2
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.1.3
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.1.4
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
FIGURE 3-4:
SCL
SDA
1996 Microchip Technology Inc.
not busy.
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
(A)
Bi-directional Mode Bus
Characteristics
BUS NOT BUSY (A)
START DATA TRANSFER (B)
STOP DATA TRANSFER (C)
DATA VALID (D)
CONDITION
START
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
ACKNOWLEDGE
ADDRESS OR
VALID
(D)
Preliminary
TO CHANGE
ALLOWED
DATA
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
eight will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.1.5
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Note:
Note:
ACKNOWLEDGE
Once switched into Bi-directional Mode, the
24LC21A will remain in that mode until
power is removed. Removing power is the
only way to reset the 24LC21A into the
Transmit-only mode.
The 24LC21A does not generate any
acknowledge
programming cycle is in progress.
(D)
bits
24LC21A
if
DS21160B-page 7
an
CONDITION
STOP
(C)
internal
(A)
Of