PXB4221 Infineon Technologies AG, PXB4221 Datasheet - Page 172

• Manufacturer Part Number: PXB4221
• Description: IWE8 Interworking Element for 8 E1/T1 Lines
• Manufacturer: Infineon Technologies AG

ut_par
ex_par
crv_par
oq_ovf
eq_ovf
ck_eme
Note: Bits 6:0 are used for tracing error events. They are set on the occurrence of an
Data Sheet
error event and reset by a microprocessor read operation.
Bits 15:10 Bits are reset upon reading of the interrupt generating register.
Parity error on UTOPIA bus
Parity error on external RAM
In order to prevent external RAM parity errors, the external RAM should
be written completely during board initialization by the microprocessor.
0 =
1 =
Parity error on clock recovery interface
0 =
1 =
Output queue overflow
0 =
1 =
Error queue overflow
0 =
1 =
Emergency mode state change on one of the emergency mode enabled
ports (see ckmo)
0 =
1 =
False
True
False
True
False
True
False
True
False
True
172
PXB4219 / PXB4220 / PXB4221
Register Description
2002-05-06