PXB4221 Infineon Technologies AG, PXB4221 Datasheet - Page 105

• Manufacturer Part Number: PXB4221
• Description: IWE8 Interworking Element for 8 E1/T1 Lines
• Manufacturer: Infineon Technologies AG

FTFRS[0:7]
RFCLK
Figure 27
5.1.4
In this mode (pin EC = 0) transmit and receive channels are synchronized.
The framer interface is clocked with an 8.192 MHz clock connected to RFCLK.
All receive channels and the channels transmitted on even ports (near-end signal with
echo) are synchronized by means of the FTFRS[0] pin. Shift exists between odd and
even FTDAT ports
FRCLK[0:7]
FRDAT[0:7]
FRMFB[0:7]
FRFRS[0:7]
FRLOS[0:7]
FTCKO[0:7]
FTDAT[0:7]
Data Sheet
RFCLK
FRDATn
FRMFB
FTDATn
B8
248
B8
248
Echo Canceller Mode (EC)
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
249
249
Framer Interface in SYM8 E1
250
250
251
251
Framer Transmit Frame Synchronization Pulse
Unused
Reference Clock
Central framer interface clock with 8.192 MHz
timeslot 31
Framer Receive Clock
Unused
Framer Receive Data
FRDAT is sampled in the middle of the bit period on the falling
edge of RFCLK
Framer Receive Multiframe Begin
Unused
Framer Receive Frame Synchronization Pulse
Unused
Framer Receive Loss of Signalling
Framer Transmit Clock
Unused
Framer Transmit Data
FTDAT is clocked with the falling edge of RFCLK:
252
252
253
253
254
254
255
255
256
256
1
1
2
2
105
3
3
timeslot 0
4
4
5
5
PXB4219 / PXB4220 / PXB4221
6
6
7
7
8
8
9
9
Interface Description
10
10
11
11
timeslot 1
12
12
13
13
2002-05-06
14
14
15
15
16
16