DS89C420 Dallas Semiconducotr, DS89C420 Datasheet - Page 42

• Manufacturer Part Number: DS89C420
• Description: Ultra-High-Speed Microcontroller
• Manufacturer: Dallas Semiconducotr

Table 15. Effect of Clock Mode on Timer Operation (in Number of Oscillator
Clocks)
x = don’t care
Ring Oscillator
A ring oscillator, which typically runs at 10MHz, allows the processor to recover instantly from the stop
mode.
When the system is in stop mode the crystal is disabled. When stop mode is removed, the crystal requires
a period of time to start up and stabilize. To allow the system to begin immediate execution of software
following the removal of the stop mode, the ring oscillator is used to supply a system clock until the
crystal startup time is satisfied. Once this time has passed, the ring oscillator is switched off and the
system clock is switched over to the crystal oscillator. This function is programmable and is enabled by
setting the RGSL bit (EXIF.1) to logic 1. When it is logic 0, the processor delays software execution until
after the 65,536 crystal clock periods. To allow the processor to know whether it is being clocked by the
ring or the crystal oscillator, an additional bit, termed the RGMD bit, indicates which clock source is
being used. When the processor is running from the ring, the clock-divide control bits (CD1 and CD0 in
the PMR register) are locked into the divide-by-1 mode (CD1:CD0 = 10b). The clock-divide control bits
cannot be changed from this state until after the system clock transitions to the crystal oscillator
(RGMD = 0).
Note: The watchdog is permanently connected to the crystal oscillator and continues to run at the
external clock rate. It is not driven by the ring oscillator.
Idle Mode
Idle mode suspends the processor by holding the program counter in a static state. No instructions are
fetched and no processing occurs. Setting the IDLE bit (PCON.0) to logic 1 invokes idle mode. The
instruction that executes this step is the last instruction prior to freezing the program counter. Once in Idle
mode, all resources are preserved but all peripheral clocks remain active, and the timers, watchdog, serial
ports, and power monitor functions continue to operate, so that the processor can exit the idle mode using
any interrupt sources that are enabled. The oscillator-detect circuit also continues to function when
enabled. The IDLE bit is cleared automatically once idle mode is exited. On returning from the interrupt
4X/2X, CD1, CD0
100
000
x01
x10
x11
MACHINE
1 (reserved)
CYCLES
1 (default)
CYCLE
OSC.
1,024
PER
0.25
0.5
12,288 4,096
OSC. CYCLES PER
00
12
12
12
TIMERS (0, 1, 2)
TxMH, TxM
CLOCK
—
01
=
1
2
4
1,024
0.25
0.5
42 of 59
1
1x
T2MH, T2M = xx
OSC. CYCLES
PER TIMER 2
GENERATOR
BAUD RATE
CLOCK
2,048
—
2
2
2
SM2 = 0
PORT CLOCK
12,288
OSC. CYCLES
PER SERIAL
12
3
6
MODE 0
—
SM2 = 1 SMOD = 0 SMOD = 1
4,096
1
2
4
OSC. CYCLES PER
CLOCK MODE 2
65,536
SERIAL PORT
64
64
64
—
32,768
32
32
32