DS89C420 Dallas Semiconducotr, DS89C420 Datasheet - Page 23

• Manufacturer Part Number: DS89C420
• Description: Ultra-High-Speed Microcontroller
• Manufacturer: Dallas Semiconducotr

External Data Memory Interface in Non-Page Mode Operation
Just like the program memory cycle, the external data memory cycle is four times slower than the internal
data memory cycle in non-page mode. A basic internal memory cycle contains one system clock and a
basic external memory cycle contains four system clocks for non-page mode operation.
The DS89C420 allows software to adjust the speed of external data memory access by stretching the
memory bus cycle. CKCON (8Eh) provides an application-selectable stretch value for this purpose.
Software can change the stretch value dynamically by changing the setting of CKCON.2–CKCON.0.
Table 6 shows the data memory cycle stretch values and their effects on the external MOVX-memory bus
cycle and the control signal pulse width in terms of the number of oscillator clocks. A stretch machine
cycle always contains four system clocks.
Table 6. Data Memory Cycle Stretch Values
As shown in Table 6, the stretch feature supports eight stretched external data-memory access cycles that
can be categorized into three timing groups. When the stretch value is cleared to 000b, there is no stretch
on external data memory access and a MOVX instruction is completed in two basic memory cycles.
When the stretch value is set to 1, 2, or 3, the external data-memory access is extended by 1, 2, or 3
stretch machine cycles, respectively. Note that the first stretch value does not result in adding four system
clocks to the RD
additional setup time and one system clock to create additional address hold time. When using very slow
RAM and peripherals, a larger stretch value (4–7) can be selected. In this stretch category, one stretch
machine cycle (4 system clocks) is used to stretch the ALE pulse width, one stretch machine cycle is used
to create additional setup, one stretch machine cycle is used to create additional hold time, and one stretch
machine cycle is added to the RD or WR strobes.
Figures 5 and 6 illustrate the timing relationship for external data-memory access in full speed (stretch
value = 0), in the default stretch setting (stretch value =1), and slow data-memory accessing
(stretch value = 4) when the system clock is in divide by one mode (CD1:CD0 = 10b).
MD2:MD0
000
001
010
011
100
101
110
111
STRETCH
/
CYCLES
WR control signals. This is because the first stretch uses one system clock to create
10
0
1
2
3
7
8
9
RD
4X/2X, CD1,
CD0 = 100
/
WR
0.5
1
2
3
4
5
6
7
PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
23 of 59
4X/2X, CD1,
CD0 = 000
10
12
14
1
2
4
6
8
4X/2X, CD1,
CD0 = X10
12
16
20
24
28
2
4
8
4X/2X, CD1,
CD0 = X11
12288
16384
20480
24576
28672
2048
4096
8192