DS89C420 Dallas Semiconducotr, DS89C420 Datasheet

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... Typical applications see a speed improvement of 10 times using the same code and crystal. The DS89C420 offers a maximum crystal speed of 33MHz, achieving execution rates million instructions per second (MIPS). ...

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... Dynamically adjustable by software DETAILED DESCRIPTION The DS89C420 is pin compatible with all three packages of the standard 8051 and includes standard resources such as three timer/counters, four 8-bit I/O ports, and a serial port. It features 16kB of in-system programmable flash memory, which can be programmed in-system from an I/O port using a built-in program memory loader ...

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Figure 1. Block Diagram Control & Sequencer Decoder IR Internal Control Bus Serial I/O Watchdog Timer & Power Manager Interrupt Internal Registers CPU Timer / 1Kx 8 Counters RAM Clock & Memory Reset Control SFRs AR ...

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Table 1. Pin Description PIN DIP PLCC TQFP 40 12 22, 23, 16 ...

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... P2.3 (A11) overcomes the weak pullup. When software writes any P2.4 (A12) port pin, the DS89C420 activates a strong pulldown that P2.5 (A13) remains on until either written or a reset occurs. Writing a P2.6 (A14) 1 after the port has been at 0 causes a strong transition driver to P2 ...

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... T0 P3.4 P3.5 T1 P3.5 P3.6 WR P3.6 RD P3.7 P3.7 External Access. Allows selection of internal or external EA program memory. Connect to ground to force the DS89C420 to use an external memory-program memory. The internal RAM is still accessible as determined by register settings. Connect use internal flash memory FUNCTION RD and WR External Interrupt 0 External Interrupt 1 ...

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... Therefore, they required the same amount of time. In the DS89C420, the MOVX instruction takes as little as two machine cycles or two oscillator cycles but the “MOV direct, direct” uses three machine cycles or three oscillator cycles. While both are faster than their original counterparts, they now have different execution times ...

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... RAM by setting the stack pointer to the desired location, although the lower bytes are normally used for working registers. I/O Ports The DS89C420 offers four 8-bit I/O ports. Each I/O port is represented by an SFR location, and can be written or read. The I/O port has a latch that contains the value written by software. Counter/Timers Three 16-bit timer/counters are available in the DS89C420. Each timer is contained in two SFR locations that can be read or written by software. The timers are controlled by other SFRs described in the “ ...

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Table 2. Special Function Registers REGISTER ADDR BIT7 P0 80h P0.7 SP 81h — — DPL 82h — DPH 83h — DPL1 84h — DPH1 85h DPS 86h ID1 PCON 87h SMOD_0 TCON 88h TF1 TMOD 89h GATE — TL0 ...

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REGISTER ADDR BIT7 — RCAP2H CBh — TL2 CCh — TH2 CDh PSW D0h CY FCNTL D5h FBUSY — FDATA D6h WDCON D8h SMOD_1 — ACC E0h EIE E8h — — B F0h EIP1 F1h — EIP0 F8h — BIT6 ...

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Table 3. SFR Reset Value REGISTER ADDR P0 80h SP 81h DPL 82h DPH 83h DPL1 84h DPH1 85h DPS 86h PCON 87h TCON 88h TMOD 89h TL0 8Ah TL1 8Bh TH0 8Ch TH1 8Dh CKCON 8Eh P1 90h EXIF ...

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REGISTER ADDR BIT7 TL2 CCh TH2 CDh PSW D0h FCNTL D5h FDATA D6h WDCON D8h ACC E0h EIE E8h B F0h EIP1 F1h EIP0 F8h BIT6 BIT5 BIT4 ...

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... The program memory ROMSIZE feature allows software to dynamically configure the maximum address of on-chip program memory. This allows the DS89C420 to act as a bootloader for an external flash or NV SRAM. It also enables the use of the overlapping external program spaces. ...

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Figure 2. Memory Map INTERNAL REGISTERS 128 Bytes SFR FF 128 Bytes Indirect Addressing Bit Addressable 20 1F Bank 3 Bank 2 Bank 1 Bank 0 00 FFFF INTERNAL MEMORY 03FF SRAM Data OR ...

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... However, the maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the DS89C420 to behave like a device with less on-chip memory. This is beneficial when overlapping external memory is used. The maximum memory size is dynamically variable. Thus, a portion of memory can be removed from the memory map to access off-chip memory, then be restored to access on-chip memory ...

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... Software selects the data pointer to be used by writing to the SEL bit (DPS.0). The DS89C420 also provides a user option for high-speed external memory access by reconfiguring the external memory interface into page mode operation. ...

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... The ROM loader also has an auto-baud feature that determines which baud rate frequencies are being used for communication and sets up the baud rate generator for communication at that frequency. When the DS89C420 is powered up and has entered its user operating mode, the ROM loader mode can be invoked at any time by forcing RST = 1, ...

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Flash programming is executed by a series of internal flash commands that are derived (by the built-in ROM loader) from data transmitted over the serial interface from a host PC. PC-based software tools that configure and load the microcontrollers are ...

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... The following sequence can be used to program the flash memory in the parallel programming mode: 1) The DS89C420 is powered up and running at a clock speed between 4MHz and 6MHz. 2) Set RST = and PSEN = 0. 3) Apply the appropriate logic combination to pins P2.6, P2.7, P3.6, and P3.7 to select one of the flash instructions shown in Table 8 ...

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... POR default setting. Erase the option control register This operation disables the watch- dog reset function on power-up. 30h = Manufacturer ID 31h = Device ID 60h = Device extension L L FCh = Verify the option control register. Bit 3 of the DOUT is the logic value of the watchdog POR. DS89C420 ...

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... The active data pointer is always selected by the SEL (DPS.0) bit. The DS89C420 offers a programmable option that allows any instructions related to data pointer to toggle the SEL bit automatically. This option is enabled by setting the toggle-select-enable bit (TSL-DPS. logic 1. Once enabled, the SEL bit is ...

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... Note that an external program fetch takes 4 system clocks, and an internal program fetch requires only 1 system clock. As illustrated in Figure 4, ALE is deasserted when executing an internal memory fetch. The DS89C420 provides a programmable user option to turn on ALE during internal program memory operation. ALE is automatically enabled for code fetch externally, independent of the setting of this option ...

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... A basic internal memory cycle contains one system clock and a basic external memory cycle contains four system clocks for non-page mode operation. The DS89C420 allows software to adjust the speed of external data memory access by stretching the memory bus cycle. CKCON (8Eh) provides an application-selectable stretch value for this purpose. ...

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Figure 5. Non-Page Mode, External Data-Memory Access (Stretch = 0, CD1:CD2 = 10) XTAL1 ALE PSEN RD WR Port 0 A MOVX Port 2 A MOVX Instruction Fetch Figure 6. Non-Page Mode, External Data-Memory Access (Stretch = 1, CD1:CD2 = ...

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... The DS89C420 supports page mode in two external bus structures. The logic value of the page mode select bits in the ACON register determines the external bus structure and the basic memory cycle in the number of system clocks ...

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The first page mode (page mode 1) external bus structure uses P2 as the primary address bus, (multiplexing both the most significant byte (MSB) and least significant byte (LSB) of the address for each external memory cycle) and P0 is ...

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The second page mode (page mode 2) external bus structure multiplexes the most significant address byte with data on P2, and uses P0 for the least significant address byte. This bus structure is used to speed up external code fetches ...

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... Port 2 Stretch External Data Memory Cycle in Page Mode The DS89C420 allows software to adjust the speed of external data memory access by stretching the memory bus cycle in page mode operation just like non-page mode operation. The following tables summarize the stretch values and their effects on the external MOVX-memory bus cycle and the control signals’ ...

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Table 9. Page Mode 1, Data Memory Cycle Stretch Values (Pages1:Pages0 = 01) STRETCH MD2:MD0 CYCLES 000 0 001 1 010 2 011 3 100 7 101 8 110 9 111 10 Table 10. Page Mode 1, Data Memory Cycle ...

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Table 11. Page Mode 2, Data Memory Cycle Stretch Values (Pages1:Pages0 = 11) STRETCH MD2:MD0 CYCLES 000 0 001 1 010 2 011 3 100 7 101 8 110 9 111 10 As shown in the previous tables, the stretch ...

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Figure 9. Page Mode 1, External Data Memory Access (Pages = 01, Stretch = 10) XTAL1 ALE PSEN Port 0 Inst Inst Port 2 LSB Addr LSB Addr ALE PSEN Port ...

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Figure 10. Page Mode 1, External Data Memory Access (Pages = 01, Stretch = 10) XTAL1 ALE PSEN Inst Inst Inst Port 0 Port 2 LSB LSB LSB MOVX Instruction Fetch ALE PSEN RD ...

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... Interrupts The DS89C420 provides 13 interrupt vector sources. All interrupts, with the exception of the power-fail, are controlled by a series combination of individual enable bits and a global enable (EA) in the interrupt enable register (IE.7). Setting logic 1 allows individual interrupts to be enabled. Setting logic 0 disables all interrupts regardless of the individual interrupt enable settings. The power-fail interrupt is controlled by its individual enable only ...

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... Unless marked in Table 12, all of these flags must be cleared by software. Timer/Counters Three 16-bit timers are incorporated in the DS89C420. All three timers can be used as either counters of external events, where 1-to-0 transitions on a port pin are monitored and counted, or timers that count oscillator cycles. Table 13 summarizes the timer functions. ...

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T0/T1 pin for 1-to-0 transitions. The mode of operation is controlled by the timer mode (TMOD) register. Each timer consists of a 16-bit register in 2 bytes, which can be found in the SFR map as TL0, ...

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Timed Access The timed access function provides control verification to system functions. The timed access function prevents an errant CPU from making accidental changes to certain SFR bits that are considered vital to proper system operation. This is achieved by ...

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... CD1 and CD0 is reserved, and has the same effect as the 10b setting, which forces the system clock into a divide by 1 mode. The DS89C420 defaults to divide-by-1 clock mode on all forms of reset. When programmed to the divide-by-1024 mode, and the switchback bit (PMR.5:SWB) is also set, the system forces the clock-divide control bits to reset automatically to the divide-by-1 mode whenever the system has detected externally enabled interrupts ...

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... interrupt is generated if the corresponding power-fail PFW transitions below V CC falls below V CC RST is first applied to the DS89C420, the processor is held in reset until MUX Selector , and can only be cleared PFW , a reset is issued internally to halt program System ...

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... When the DS89C420 enters stop mode, the bandgap, reset comparator, and power-fail interrupt comparator are automatically disabled to conserve power, if the BGS (EXIF.0) bit is set to a logic 0. This is the lowest power mode. If BGS is set to a logic 1, the bandgap reference, reset comparator, and the power-fail comparator are powered up, although in a reduced fashion, while in stop mode ...

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... Oscillator-Fail Detect The DS89C420 incorporates an oscillator fail-detect circuit that, when enabled, causes a reset if the crystal oscillator frequency falls below 20kHz and holds the chip in reset with the ring oscillator operating. The circuit is enabled by setting the OFDE (PCON.4) bit to a logic 1. The OFDE bit is only cleared from a logic logic power-fail reset or by software ...

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SWB is set. Note that the serial port activity, as related to the switchback, is independent of the serial port interrupt relationship. Any attempt to change the clock divider to the divide-by-1024 mode while the serial port ...

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Table 15. Effect of Clock Mode on Timer Operation (in Number of Oscillator Clocks) OSC. CYCLES 4X/2X, CD1, CD0 PER MACHINE CYCLE 100 0.25 000 0.5 x01 1 (reserved) x10 1 (default) x11 1,024 x = don’t care Ring Oscillator ...

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... Serial I/O The DS89C420 provides a serial port (UART) that is identical to the 80C52. In addition, it includes a second hardware serial port that is a full duplicate of the standard one. This port optionally uses pins P1.2 (RXD1) and P1.3 (TXD1) and has duplicate control functions included in new SFR locations. ...

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... UNITS 4.5 5.0 5.5 V 4.2 4.375 4.6 V 3.95 4.125 4.35 V 100 150 -0.3 +0 0.15 0.45 V 0.15 0.45 V 2.4 V 2.4 V 2.4 V 2.4 V -55 µA -650 µA -10 +10 µA -300 +300 µA 50 170 k DS89C420 NOTES 12 ...

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Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground. Note 3: Active current is measured with a 33MHz clock source driving XTAL1, V Note 4: Idle mode current ...

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... CLCL CLCL t t STC3 STC3 0. 0. CLCL CLCL 0. 0. CLCL CLCL t t STC4 STC4 0. 0. CLCL CLCL t t STC4 STC4 2. CLCL 1. 0. CLCL CLCL CLCL CLCL DS89C420 UNITS NOTES MAX 33 MHz 2. CLCL ns ns ...

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... CLCL CLCL t t STC1 STC1 - CLCL CLCL t t STC1 STC1 CLCL 2. CLCL + t STC1 CLCL t STC1 DS89C420 UNITS NOTES MAX CLCL CLCL CLCL 3. CLCL CLCL STC1 ...

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... STC2 STC2 1. CLCL CLCL t t STC2 STC2 1. CLCL CLCL t t STC5 STC5 - STC2 STC2 STC2 STC2 DS89C420 UNITS NOTES MAX 3. CLCL STC1 0. CLCL STC2 STC2 ...

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Note 1: The system clock frequency is dependent on the oscillator frequency and the setting of the clock-divide control bits (CD1 and CD0) and the crystal 2 X multiplier control bits (4X/ and CTM) in the PMR register. The term ...

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Figure 12. Non-Page Mode Timing XTAL1 t CLCL ALE t AVLL2 t AVLL PSEN t LLPL t PXIX LLIV t LLAX Port 0 LSB MOVX t PXIZ Port 2 MSB t LHLL t AVLL3 t LLAX3 t ...

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Figure 13. Page-Mode 1 Timing XTAL1 t CLCL ALE t AVLL2 PSEN AVIV2 Port 0 MOVX OPCODE Port 2 LSB LSB LSB Figure 14. Page-Mode 2 Timing XTAL1 t CLCL ALE t AVLL t AVLL2 PSEN t ...

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... QVXH XHQX XHDX 0 t XHDV UNITS VARIABLE MAX MIN MAX 12t CLCL 4t CLCL 10t - CLCL 100 CLCL CLCL t - 100 CLCL 0 0 200 10t 40 3t CLCL DS89C420 MAX CLCL ns 100 - 50 ...

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Figure 15. Serial Port Timing SERIAL PORT (SYNCHRONOUS MODE) SM2 = 1 TDX CLOCK = XTAL FREQ/4 ALE PSEN t QVXH WRITE TO SBUF RXD DATA OUT TXD CLOCK TI WRITE TO SCON TO CLEAR RI RXD DATA IN TXD ...

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POWER CYCLE TIMING CHARACTERISTICS (V = 4.5V to 5.5V -40°C to +85°C) (Note PARAMETER Crystal Startup Time Power-On Reset Delay Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: ...

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PACKAGE DRAWINGS 40-PIN PDIP (600MIL) PKG 40-PIN DIM MIN A — A1 0.015 A2 0.140 b 0.014 c 0.008 D 1.980 E 0.600 E1 0.530 e 0.090 L 0.115 56–G5000–000 Dimensions are in inches (in). eB 0.600 MAX 0.200 — ...

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PLCC Note 1: Pin 1 identifier to be located in zone indicated. Note 2: Controlling dimensions are in inches (in ...

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TQFP ...

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... PLCC ORDERING INFORMATION PART TEMP RANGE DS89C420-MCL 0°C to +70°C DS89C420-QCL 0°C to +70°C DS89C420-ECL 0°C to +70°C DS89C420-MNL -40°C to +85°C DS89C420-QNL -40°C to +85°C DS89C420-ENL -40°C to +85°C TOP VIEW MAX. CLOCK SPEED (MHz ...

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... REVISION HISTORY 1) Original issue, 092200. 2) Added errata, 122601. (See www.maxim-ic.com/errata 3) Official product introduction release, 042702. 4) Inserted Table 17, 051302. 5) Removed (Min Operating Voltage) from DC Electrical Characteristics; inserted diagram of ROM loader interface circuit, 103102. for more details DS89C420 ...