FM20L08_07 RAMTRON [Ramtron International Corporation], FM20L08_07 Datasheet - Page 5

• Manufacturer Part Number: FM20L08_07
• Description: 1Mbit Bytewide FRAM Memory - Industrial Temp.
• Manufacturer: RAMTRON [Ramtron International Corporation]

Supply Voltage Monitor
An internal voltage monitor circuit continuously
checks the V
the specified threshold V
/LVL signal to an active-low state. The FM20L08
locks out access to the memory when V
the trip voltage. This prevents the system from
accessing memory when V
inadvertently corrupting the data. The /LVL signal
should not be used as a system reset signal because
the system host may attempt to write data to the
FM20L08 below its specified operating voltage. The
/LVL pin may be used as a status indicator that the
memory is locked out.
On power up, the /LVL signal will begin in a low
state signifying that V
will remain low as long as V
Once V
creating the delay t
the /LVL signal will go high or inactive. At this time
the memory can be accessed. The memory is ready
for access prior to t
Specifications section. The /LVL signal will remain
high until V
Software Write Protection
(Applies only to “-TG1” device. The –TG device does
not have this Write Protect feature. See Ordering
Information on page 1)
The 128Kx8 address space is divided into 8 sectors
(blocks) of 16Kx8 each. Each sector can be
individually software write-protected and the settings
are nonvolatile. A unique address and command
sequence invokes the write protection mode.
To modify write protection, the system host must
issue six read commands and two write commands.
The specific sequence of read addresses must be
provided in order to access to the write protect mode.
Following the read address sequence, the host must
write a data byte that specifies the desired protection
state of each sector. For confirmation, the system
must then write the complement of the protection byte
immediately following the protection byte. Any error
that occurs including read addresses in the wrong
order, issuing a seventh read address, or failing to
complement the protection value will leave the write
protection unchanged.
The
addresses, taking no action until the write-protect
read/write sequence occurs. During the address
Rev. 1.72
May 2007
write-protect
DD
rises above V
DD
DD
drops below the threshold.
supply voltage. When V
PULV
state
DD
PU
. Once this delay has elapsed,
TP
is below the V
as shown in the Electrical
, a hold-off timer will begin
TP
, the monitor asserts the
machine
DD
DD
is below that level.
is too low and
TP
monitors all
DD
threshold. It
DD
is below
is below
sequence, each read will occur as a valid operation and
data from the corresponding addresses will be driven
onto the data bus. Any address that occurs out of
sequence will cause the software protection state
machine to start over. After the address sequence is
completed, the next operation must be a write cycle.
The data byte contains the write-protect settings. This
value will not be written to the memory array, so the
write address is ignored. Rather the byte will be held
pending the next cycle, which must be a write of the
data complement to the protection settings. If the
complement is correct, the write protect settings will be
updated. If not, the process is aborted and the address
sequence starts over. The data value written after the
correct six addresses will not be entered into memory.
The protection data byte consists of 8-bits, each
associated with the write protect state of a sector.
Setting a bit to 1 write protects the corresponding
sector; a 0 enables writes for that sector. The following
table shows the write-protect sectors with the
corresponding bit that controls the write-protect setting.
Write Protect Sectors – 16K x8 blocks
The write-protect address sequence follows:
The address sequence provides a very secure way of
modifying the protection. The correct address sequence
has a 1 in 5 x 10
flow chart of the entire write protect operation is shown
in Figure 2. As mentioned above, write-protect settings
are nonvolatile. The factory default is unprotected.
Sector 7
Sector 6
Sector 5
Sector 4
Sector 3
Sector 2
Sector 1
Sector 0
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. 00000h
* If /CE is low entering the sequence, then an
address of 00000h must precede 05555h.
05555h *
1AAAAh
03333h
1CCCCh
100FFh
0FF00h
1AAAAh
1CCCCh
0FF00h
30
1FFFFh – 1C000h
1BFFFh – 18000h
17FFFh – 14000h
13FFFh – 10000h
0FFFFh – 0C000h
0BFFFh – 08000h
07FFFh – 04000h
03FFFh – 00000h
chance of occurring accidentally. A
FM20L08 - Industrial Temp.
Page 5 of 14