FM21L16_11 RAMTRON [Ramtron International Corporation], FM21L16_11 Datasheet
FM21L16_11
Related parts for FM21L16_11
FM21L16_11 Summary of contents
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Pre-Production FM21L16 2Mbit F-RAM Memory Features 2Mbit Ferroelectric Nonvolatile RAM Organized as 128Kx16 Configurable as 256Kx8 Using /UB, / Read/Write Cycles NoDelay™ Writes Page Mode Operation to 33MHz Advanced High-Reliability Ferroelectric Process SRAM Compatible Industry Std. 128Kx16 SRAM ...
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A(16: Control 2 UB, LB Logic OE ZZ Pin Description Pin Name Type Pin Description A(16:0) Input Address inputs: The 17 address lines select one of 131,072 words in the F-RAM array. The lowest two address lines A(1:0) ...
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Functional Truth Table /CE /WE A(16: Change L H Change Change X X Notes: 1) H=Logic High, L=Logic Low, V=Valid Data, X=Don’t ...
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Overview The FM21L16 is a wordwide F-RAM memory logically organized as 131,072 x 16 and accessed using an industry standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation ...
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Precharge Operation The precharge operation is an internal condition in which the state of the memory is being prepared for a new access. Precharge is user-initiated by driving the /CE signal high. It must remain high for at least the ...
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A flow chart of the entire write protect operation is shown in For example, the following sequence write-protects addresses from 0C000h to 13FFFh ...
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Figure 4. Sequence to Set Write-Protect Blocks Note: This sequence requires t Figure 5. Sequence to Read Write-Protect Settings Note: This sequence requires t Rev. 2.0 Apr. 2011 ≥ 10ns and address must be stable while /CE is low. AS ...
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SRAM Drop-In Replacement The FM21L16 has been designed drop-in replacement for standard asynchronous SRAMs. The device does not require /CE to toggle for each new address. /CE may remain low for as long as 10µs. While /CE ...
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Electrical Specifications Absolute Maximum Ratings Symbol Description V Power Supply Voltage with respect Voltage on any signal pin with respect Storage Temperature STG T Lead Temperature (Soldering, 10 seconds) LEAD V Electrostatic ...
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Read Cycle AC Parameters ( Symbol Parameter t Read Cycle Time RC t Chip Enable Access Time CE t Address Access Time AA t Output Hold Time OH t Page Mode ...
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Power Cycle and Sleep Mode Timing (T Symbol Parameter t Power Up (after Last Write (/WE high) to Power Down Time Rise Time Fall Time /ZZ ...
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Page Mode Read Cycle Timing Although sequential column addressing is shown not required. Write Cycle Timing 1 (/WE-Controlled) Write Cycle Timing 2 (/CE-Controlled) CE A(17:0) WE DQ(15:0) UB/LB Rev. 2.0 Apr. 2011 Note: /OE (not shown) is low ...
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Write Cycle Timing 3 (/CE low) Note: /OE (not shown) is low only to show effect of / pins Page Mode Write Cycle Timing Although sequential column addressing is shown not required. Power Cycle and Sleep ...
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Mechanical Drawing 44-pin TSOP-II (Complies with JEDEC Standard MS-024g Var. AC) Pin 1 0.45 0.30 0.80 BSC 10.16 BSC 11.96 11.56 TSOP-II Package Marking Scheme Legend: XXXXXX= part number, S= speed, P=package RAMTRON XXXXXXX-S-P LLLLLL= lot code, YY=year, WW=work week ...
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Revision History Revision Date 1.0 9/24/2007 1.1 12/12/2007 1.2 12/22/2009 2.0 4/4/2011 Rev. 2.0 Apr. 2011 Summary Initial release. Added package MSL rating and placeholder for ESD ratings. Lowered I limit. Added UB/LB signals to timing diagrams and added DD ...