GAL20LV8ZD-25QJ LATTICE [Lattice Semiconductor], GAL20LV8ZD-25QJ Datasheet - Page 6

• Manufacturer Part Number: GAL20LV8ZD-25QJ
• Description: Low Voltage, Zero Power E2CMOS PLD Generic Array Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

In the Complex mode, macrocells are configured as output only or
I/O functions.
Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 18 & 26) do not have input capability. De-
signs requiring eight I/Os can be implemented in the Registered
mode.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Complex Mode
XOR
XOR
6
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 2 and
16 are always available as data inputs into the AND array.
Pin 5 is used as dedicated power-down pin on GAL20LV8ZD. It
cannot be used as functional input.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 19 through Pin 25 are configured to this function.
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 18 and Pin 26 are configured to this function.
Specifications GAL20LV8ZD