GAL20LV8ZD-25QJ LATTICE [Lattice Semiconductor], GAL20LV8ZD-25QJ Datasheet - Page 14

• Manufacturer Part Number: GAL20LV8ZD-25QJ
• Description: Low Voltage, Zero Power E2CMOS PLD Generic Array Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

3-state levels are measured 0.5V from steady-state active
level. 3-state to active transitions are measured at (Voh - 0.5)
V and (Vol + 0.5) V.
Output Load Conditions (see figure)
f
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Descriptions
Test Condition
A
B
C
Note: fmax with external feedback is calculated from
measured tsu and tco.
Note: fmax with no feedback may be less than 1/(twh
+ twl). This is to allow for a clock duty cycle of other
than 50%.
f
Active High
Active Low
Active High
Active Low
max with External Feedback 1/(
L O G I C
A R R A Y
LOGIC
ARRAY
t
su +
f
t
max with No Feedback
s u
t
h
270
270
270
270
270
R
1
R EG I S T E R
REGISTER
C L K
CLK
220
220
220
220
220
R
2ns 10% – 90%
2
t
GND to 3.0V
t
See Figure
su+
c o
1.5V
1.5V
t
co)
35pF
35pF
35pF
5pF
5pF
C
L
14
Specifications GAL20LV8ZD
FROM OUTPUT (O/Q)
UNDER TEST
Note: tcf is a calculated value, derived by subtracting
tsu from the period of fmax w/internal feedback (tcf
= 1/fmax - tsu). The value of tcf is used primarily
when calculating the delay from clocking a register
to a combinatorial output (through registered feed-
back), as shown above. For example, the timing
from clock to a combinatorial output is equal to tcf
+ tpd.
*C
f
max with Internal Feedback 1/(
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
LOGIC
ARRAY
R
2
+3.3V
t
cf
t
pd
REGISTER
R
CLK
1
C *
t
su+
L
TEST POINT
t
cf)