GAL20LV8ZD-25QJ LATTICE [Lattice Semiconductor], GAL20LV8ZD-25QJ Datasheet - Page 16

• Manufacturer Part Number: GAL20LV8ZD-25QJ
• Description: Low Voltage, Zero Power E2CMOS PLD Generic Array Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

Circuitry within the GAL20LV8ZD provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
Power-Up Reset
Input/Output Equivalent Schematic
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Typical Input
Vcc
FEEDBACK/EXTERNAL
INTERNAL REGISTER
OUTPUT REGISTER
t
pr, 10 s MAX). As a result,
Q - OUTPUT
Vcc
CLK
Vcc
Vcc
Vcc (min.)
16
asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the GAL20LV8ZD.
First, the V
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of
normal system operation, avoid clocking the device until all input
and feedback path setup times have been met. The clock must
also meet the minimum pulse width requirements.
t
pr
Specifications GAL20LV8ZD
Data
Output
CC
Tri-State
Control
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Feedback
rise must be monotonic. Second, the clock input
t
wl
t
su
Typical Output
Vcc
Feedback
(To Input Buffer)
PIN
PIN
t
pr time. As in