HT82V46 HOLTEK [Holtek Semiconductor Inc], HT82V46 Datasheet - Page 6

• Manufacturer Part Number: HT82V46
• Description: 16-Bit, 45MSPS, 3-Channel CCD/CIS Analog Signal Processor
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Note: 1. Parameters are measured at 50% of the rising/falling edge.
Function Description
Introduction
The HT82V46 can sample up to three inputs, namely
VINR, VING and VINB, simultaneously. The device
then processes the sampled video signal with respect
to the video reset level or an internally/externally
generated reference level for signal processing. Each
processing channel consists of an Input Sampling
block with optional Reset Level Clamping (RLC)
and Correlated Double Sampling (CDS), an 8-bit
programmable offset DAC and a 9-bit Programmable
Gain Amplifier (PGA). The ADC then converts each
resulting analogue signal to a 16-bit digital word.
The digital output from the ADC is presented on an
8-bit wide bus. On-chip control registers determine
the configuration of the device, including the offsets
and gains applied on each channel. These registers are
programmable via a serial interface.
Internal Power-On-Reset (POR) Circuit
Internal POR Circuit is powered by AV
reset digital logic into a default state after power-
up. POR active from 0.6V
at 1.2V
powered before DV
back to 0.6V
the contents of the control registers are at their default
values before carrying out any other register writes it
is recommended software reset for every time power
is cycled.
Rev. 1.10
Serial Control Interface
t
t
t
t
t
t
t
t
t
t
t
SCK
SCKH
SCKL
SDIS
SDIH
CKFENR
ENFCKR
SEN
ENFSD7
CKFSD6
CKFOD7
Symbol
2. In 1-channel mode, if the CDS2 falling edge is placed more than 3ns before the rising edge of ADCK, the
Typ.
output amplitude of the HT82V46 will decrease.
of AV
SCK Period
SCK High
SCK Low
SDI Set-up Time
SDI Hold Time
SCK Falling to SEN Rising
SEN Falling to SCK Rising
SEN Pulse Width
SEN Falling to OD7/SDO Output the
D7 of Register Data
SCK Falling to OD7/SDO Output the
D6 of Register Data
SCK Falling to OD7/SDO Output OD7
Typ.
then POR will active again. To ensure
DD
(or 0.7V
DD
). And when AV
Parameter
Typ.
of AV
Typ.
of DV
DD
and release
DD
DD
DD
and used
or DV
if AV
Test Conditions
DD
DD
6
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Power Management
The device default is fully enabled. The Register Bit
EN allows the device to be fully powered down when
set low. Individual blocks can be powered down using
the bits in Setup Register 5. When in 1CH or 2CH
mode the unused input channels are automatically
disabled to reduce power consumption.
References
The ADC reference voltages are derived from an
internal bandgap reference, and buffered to pins
REFT and REFB, where they must be decoupled to
ground. Pin CML is driven by a similar buffer, and
also requires decoupling. The output buffer from the
RLCDAC also requires decoupling at pin VRLC/
VBIAS.
CDS/Non-CDS Processing
For CCD type input signals, containing a fixed
reference level, the signal may be processed using
Correlated Double Sampling (CDS), which will
remove pixel-by-pixel common mode noise. With
CDS processing the input waveform is sampled at
two different points in time for each pixel, once
during the reference level and once during the video
level. To sample using CDS, register bit CDS must
be set to 1 (default). This causes the signal reference
to come from the video reference level as shown in
Figure 1. The video sample is always taken on the
falling edge of the input CDS2 signal (C2
mode the reference level is sampled on the falling
Min.
83.3
37.5
37.5
12
12
60
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6
6
Typ.
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November 24, 2011
Max.
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―
―
―
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30
30
30
HT82V46
S
). In CDS-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns