HT82V46 HOLTEK [Holtek Semiconductor Inc], HT82V46 Datasheet - Page 22

• Manufacturer Part Number: HT82V46
• Description: 16-Bit, 45MSPS, 3-Channel CCD/CIS Analog Signal Processor
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Rev. 1.10
DAC value
DAC value
DAC value
DAC value
register 6
PGA gain
PGA gain
PGA gain
PGA gain
PGA gain
PGA gain
Register
(Green)
(Green)
(Green)
(RGB)
(RGB)
Setup
(Blue)
(Blue)
(Red)
(Red)
(Red)
ID
Bit No.
3:1
7:4
3:0
7:0
7:0
7:0
7:0
7:0
7:0
0
4
5
6
7
0
0
0
0
C2DLY[2:0]
DACG[7:0]
PGAG[8:1]
DACR[7:0]
DACB[7:0]
PGAR[8:1]
Reserved
Reserved
DAC[7:0]
PGAR[0]
PGAG[0]
CLPCTL
PGAB[0]
C2POS
RLCEN
C2DET
PGA[0]
ID[3:0]
Name
POR.
0000
000
0D
0D
0
0
1
0
0
0
0
0
0
0
0
0
0
0
When WS=0 this register bit has no effect.
When WS=1.
When WS=0 or C2DET=0 these bits have no effect.
The C2DLY bits set a programmable delay from the detected edge of
the signal applied to the CDS2 pin. The internally generated pulse is
delayed by C2DLY ADCK periods from the detected edge.
When WS=0 or C2DET=0 this bit has no effect
When WS=1 and C2DET=1 this bit controls whether positive or
negative edges on the CDS2 input pin are detected.
Reset level clamping enable. When set RLCEN is enabled. The
method of clamping is determined by CLPCTL and WS.
In “WS” mode clamping will still occur on every pixel at a time defined
by the CDSREF[1:0] bits.
This bit has no effect if WS=1. See Table 3 for more information.
Must be set to 0.
Must be set to 0.
ID[3:0] these bits are storable and can be written from 0000 to 1111
values. But note that ID[3:0] will be cleared to 0000 after Power-On-
Reset.
Red channel 8-bit offset DAC MSB value.
Green channel 8-bit offset DAC MSB value.
Blue channel 8-bit offset DAC MSB value.
Write to this register will cause the R, G and B offset DAC MSB
registers to be overwritten by the new value.
This register bit forms the LSB of the red channel PGA gain code.
PGA gain is determined by combining this register bit and the 8 MSBs
contained in register address 28 hex.
This register bit forms the LSB of the green channel PGA gain code.
PGA gain is determined by combining this register bit and the 8 MSBs
contained in register address 29 hex.
This register bit forms the LSB of the blue channel PGA gain code.
PGA gain is determined by combining this register bit and the 8 MSBs
contained in register address 2A hex.
Writing a value to this location causes red, green and blue PGA LSB
gain values to be overwritten by the new value.
Red PGA gain setting register. 0.66+PGAR[8:0]*7.34/511
Green PGA gain setting register. 0.66+PGAG[8:0]*7.34/511
0= Normal operation, signal on CDS2 input pin is applied directly to
1= Programmable CDS2 detect circuit is enabled. An internal
0= Negative edge on CDS2 pin is detected and used to generate
1= Positive edge on CDS2 pin is detected and used to generate
0= RLC switch is controlled directly from CDS1 input pin.
1= RLC switch is controlled by logical combination of CDS1 and
timing control block.
synchronization pulse is generated from signal applied to CDS2
input pin and is applied to timing control block on place of CDS2.
internal timing pulse.
internal timing pulse.
CDS1= 0: switch is open
CDS1= 1: switch is close
CDS2.
CDS1 & CDS2=0 : switch is open.
CDS1 & CDS2=1 : switch is close.
22
Description
November 24, 2011
HT82V46