HT82V46 HOLTEK [Holtek Semiconductor Inc], HT82V46 Datasheet - Page 14

• Manufacturer Part Number: HT82V46
• Description: 16-Bit, 45MSPS, 3-Channel CCD/CIS Analog Signal Processor
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Summaries of the RLC Switch Control
Rev. 1.10
Analog
Input is DC coupled
and within supply
range
Input video signal
has a suitable
reference level
Pixel reference level
not stable or need
to clamp the black
pixels of video period
Using “WS” mode
Using auto-cycling
in “WS” mode
ADCK
CDS2
CDS1
Input
CLP
Option
RLC is not enabled.
RLC switch is always open.
RLC switch is controlled by CDS1 pin.
CDS1=0/1 : switch is open/closed
CDS2 is normal, and CDS1 is used to indicate
black pixels location. RLC switch is controlled
by CDS1 and CDS2 logical combination.
CDS1 & CDS2=0/1: switch is open/closed
CDS1 pin as RLC/ACYC pin, and the
reference sample clock is gated by the “WS”
internal timing generator, see Figure 11.
CLP is an internal clamp switch control signal.
CLP=0/1 : clamp switch open/closed
CDS1 pin as auto-cycling control and can’t be
clamp control signal.
CLPCTL controls whether RLC is enabled or
not. CLPCTL=0/1 : RLC is disabled/ enabled;
see Figure 11.
unstable Ref. level
Figure 12 Line-Clamping RLC Operation (Non-CDS Only)
Table 3 The Options for the Control of RLC Switch
Dummy or Black pixel
RLC control
14
WS
Video level
X
0
0
1
1
CLPCTL RLCEN ACYC LNBYLN
X
X
0
1
0
1
Register Bit
X
0
1
1
1
November 24, 2011
X
X
X
X
1
HT82V46
X
X
X
X
1