HT82V46 HOLTEK [Holtek Semiconductor Inc], HT82V46 Datasheet

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... D converter. The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS active pixel sensors, which do not require CDS. The 16-bit digital output is available in 8-bit wide multiplexed format. The internal registers are programmed through a 4-wire serial interface, which provides gain, offset and operating mode adjustments. The HT82V46 operates from a single 3.3V power supply, typically consumes 528mW of power. REFT REFB CML Bandgap Reference ...

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... Description 2 HT82V46 November 24, 2011 ...

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... DD ― ― ― I =1mA DV -0.5 ― =1mA ― ― OL ― ― ― ― ― ― ― ― ― 3 HT82V46 -0. +4. -0. +0. Max. Unit 3.6 V 3.6 V ― V 0.2* μA 1 μA ― pF ― μA ― ...

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... CDACRNG=0 0.4 ― CDACRNG=1 0.4 CDACRNG=0 3.00 ― CDACRNG=1 2.05 ― -0.5 ― ― ― +/-1 ― ― 8 ― ― 2.04 Code 00(hex) -260 ― Code FF(hex) +260 4 HT82V46 Max. Unit ― MSPS V P-P ― V P-P V P-P ― V P ― mV ― mV ― LSB ― LSB ― % LSB rms ― ...

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... HT82V46 Max. Unit ― bits V/V ― V/V ― V ― bits ― MSPS V ― V ― mA ― mA ― mA ― μA Max. Unit ― ns ― ...

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... DD during the reference level and once during the video level. To sample using CDS, register bit CDS must be set to 1 (default). This causes the signal reference to come from the video reference level as shown in Figure 1. The video sample is always taken on the falling edge of the input CDS2 signal (C2 mode the reference level is sampled on the falling 6 HT82V46 Max. Unit ― ns ― ns ― ns ― ns ― ns ― ns ― ...

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... HT82V46 can accommodate this type of input by setting the LNBYLN register bit high. When in this mode the green and blue input PGAs are disabled to save power. The analogue input signal should ...

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... Pixel n+1 Pixel n C2FADR t ADC n-2 8 HT82V46 Mode Blue V 3-channel 1 X 2-channel 1-channel ― Invalid ― Invalid t PR3 n-1 November 24, 2011 ...

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... Rev. 1.10 Pixel n+1 Pixel n PR2 C2FADR n-3 Pixel n+1 Pixel n+2 t PR1 ADFC2R ADC n-7 n-6 9 HT82V46 Pixel n n-2 n-1 Pixel n+3 ADFC2F n-5 November 24, 2011 ...

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... For Colour Line-by-Line, set Register Bit LNBYLN. For input selection, refer to Table 1, Colour Selection Description in Line-by-Line mode. Rev. 1. Register Bit CDSREF[1:0] WS MODE4 7.5 ― 0 7.5 ― 22 22.5 ― HT82V46 2CH 1CH CDS November 24, 2011 ...

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... HB LB DLY[1: DLY[1: DLY[1: DLY[1: DLY[1: HT82V46 ...

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... Figure 9 MODE4 : 1-channel Line-by-Line Rev. 1. DLY[1: DLY[1: DLY[1: DLY[1: DLY[1: DLY[1: HT82V46 November 24, 2011 ...

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... CDS1 input pin to go high during the black pixels only. Alternatively it is possible to use CDS1 to identify the black pixels and enable the clamp at the same time as the input is being sampled (i.e. when CDS2 is high and CDS1 is high). This mode is enabled by setting CLPCTL=1 and the operation is shown in Figure 12. RLC switch closed when CDS1 = 1 13 November 24, 2011 HT82V46 ...

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... CLPCTL=0/1 : RLC is disabled/ enabled; see Figure 11. Table 3 The Options for the Control of RLC Switch Rev. 1.10 Video level Register Bit WS CLPCTL RLCEN ACYC LNBYLN November 24, 2011 HT82V46 ...

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... INVOD=0 D [15:0]= D [15: • INVOD [15:0]= 65535 − D [15: Output Formats The output from the HT82V46 can be presented in several different formats under control of the ODFM[1:0] register bits as shown in Figure 14. 15 HT82V46 V CBOT ) x 65535) + 32767 65535) + 65535 65535 1.2V) FS November 24, 2011 ...

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... VRLC/VBIAS pin RLC NB1 NB4 NB3 NB2 NB1 NB4 NB4~NB1 : Nibble (NB4 is the most significant) 16 HT82V46 Output Invert Block D2 OD[7: 65535 D – INVOD NB3 NB2 November 24, 2011 ...

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... SCK. SDO/OD[7] is shared pin, therefore OEB pin should always be held low and the OPD register bit should be set low when register read-back data is expected on this pin. The next word may be read in to SDI while the previous word is still being output on SDO/OD[7] pin. Note: To ensure all registers are set to their default values it is recommended that a software-reset is carried out after the power-up sequence, before writing to any other register. D[7:0] t CKFENR t ENFCKR t ENFSD7 t CKFSD6 D[5: HT82V46 t CKFOD7 D0 November 24, 2011 ...

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... INTM[1:0] CMLPD REFPD CDACPD ADCPD CLPCTL RLCEN C2POS C2DLY[2: DACR[7:0] DACG[7:0] DACB[7:0] DAC[7: PGAR[8:1] PGAG[8:1] PGAB[8:1] PGA[8:1] 18 HT82V46 1CH CDS EN INVOD ODFM[1:0] CDAC[3:0] ACYC LNBYLN BPD GPD RPD C2DET ID[3:0] PGAR[0] PGAG[0] PGAB[0] PGA[0] November 24, 2011 ...

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... Set this bit when operating in “WS” MODE 4. 0= Other mode 1= “WS” MODE 4 Makes the HT82V46 timing to the other operating mode selection 0= Normal timing 1= Enable “WS” timing. Requires double rate ADCK and pixel rate CDS2 input. CDS1 pin performs same function as RLC/ACYC pin. ...

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... Write this register will causes all function to be reset recommended that a software reset be performed after a power on before any other register writes. Write this register will causes the auto-cycle counter to reset to VINR. This function is only required when LNBYLN=1. 20 HT82V46 ), thus changing the 23.5T 26 ...

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... When set powers down 4-bit RLCDAC, setting the output to a high impedance state and allowing an external reference to be driven in on the VRLC/VBIAS pin. When set disables REFT, REFB buffers to allow external references to be used. When set disable CML buffer to allow an externa reference to be used. Must be set HT82V46 November 24, 2011 ...

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... PGA gain is determined by combining this register bit and the 8 MSBs contained in register address 2A hex. Writing a value to this location causes red, green and blue PGA LSB gain values to be overwritten by the new value. Red PGA gain setting register. 0.66+PGAR[8:0]*7.34/511 Green PGA gain setting register. 0.66+PGAG[8:0]*7.34/511 22 HT82V46 November 24, 2011 ...

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... SDI Interface Control 9 SEN 4 OEB Note: 1. All de-coupling capacitors should be fitted as close to HT82V46 as possible. 2. AVSS and DVSS should be connected as close to HT82V46 as possible. Rev. 1.10 Description Blue PGA gain setting register. 0.66+PGAB[8:0]*7.34/511 A write to this register will cause R, G and B PGA gain registers to be overwritten by the new value. AVDD ...

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... Nom. ― ― ― ― ― 0.026 ― ― ― ― Dimensions in mm Nom. ― ― ― ― ― 0.65 ― ― ― ― 24 HT82V46 0 Max. 0.323 0.220 0.013 0.413 0.079 ― ― 0.037 0.008 8° Max. 8.20 5.60 0.33 10.50 2.00 ― ― 0.95 0.21 8° November 24, 2011 ...

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... Reel Dimensions SSOP 28S (209mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.10 , Dimensions in mm 330.0±1.0 100.0±1.5 +0.5/-0.2 13.0 2.0±0.5 +0.3/-0.2 28.4 31.1 (max.) 25 November 24, 2011 HT82V46 + ...

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... Dimensions in mm 24.0±0.3 12.0±0.1 1.75±0.10 11.5±0.1 +0.1/-0.00 1.5 +0.25/-0.00 1.50 4.0±0.2 2.0±0.1 8.4±0.1 10.65±0.10 2.4±0.1 0.30±0.05 21.3±0.1 26 HT82V46 November 24, 2011 ...

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... Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at holtek.com.tw. Rev. 1.10 27 November 24, 2011 HT82V46 http://www. ...