HT82V46 HOLTEK [Holtek Semiconductor Inc], HT82V46 Datasheet - Page 15

• Manufacturer Part Number: HT82V46
• Description: 16-Bit, 45MSPS, 3-Channel CCD/CIS Analog Signal Processor
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Offset Adjust and Programmable Gain
The output from the CDS block is a differential
signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by
a 8-bit PGA. The gain and offset for each channel are
independently programmable by writing to control
bits DAC[7:0] and PGA[7:0]. In colour line-by-line
mode the gain and offset coefficients for each colour
can be multiplexed in order (Red → Green → Blue →
Red…) by pulsing the CDS1 pin, or controlled via the
ACYC and INTM[1:0] bits. Refer to the Line-by-Line
Operation section for more details.
ADC Input Black Level Adjust
The output from the PGA can be offset to match the
full-scale range of the differential ADC (2 * (V
V
Negative-going Input Cideo Signals
The black level (zero differential) output from the
PGA should be offset to the top of the ADC range by
setting register bits PGAFS[1:0]=10. This will give
an output code of FFFF (hex) from the HT82V46 for
zero input. If code zero is required for zero differential
input then the INVOD bit should be set.
Positive-going Input Video Signals
The black level should be offset to the bottom of the
ADC range by setting PGAFS[1:0]=11. This will give
an output code of 0000 (hex) from the HT82V46 for
zero input.
Bipolar Input Video Signals
It’s accommodated by setting PGAFS[1:0]=00 or
PGAFS[1:0]=01. Zero differential input voltage gives
mid-range ADC output, 7FFF (hex).
Signal Flow Summary
See Figure13 for overall signal flow diagram.
Input Sampling Block
• When CDS=1
• When CDS=0
Rev. 1.10
RB
The previously sampled reference level V
subtracted from the input video V
The simultaneously sampled voltage on pin
VRLC/VBIAS is subtracted instead.
)).
V
V
1
1
= V
= V
IN
IN
− V
− V
RLC
RL
IN
.
RL
is
RT
-
15
Where
Offset DAC Block
The resultant signal
output.
PGA Block
The signal is then multiplied by the PGA gain.
ADC Block
The analogue signal is then converted to a 16-bit
unsigned number, with input range configured by
PGAFS[1:0].
Output Invert Block
The polarity of the digital output may be inverted by
control bit INVOD.
Output Formats
The output from the HT82V46 can be presented
in several different formats under control of the
ODFM[1:0] register bits as shown in Figure 14.
• PGAFS[1:0]=0X
• PGAFS[1:0]=10
• PGAFS[1:0]=11
• INVOD=0
• INVOD=1
♦
♦
D
D
D
Where
(LOWREF=0 / 1 then
D
D
V
2
2
2
1
1
1
If CDACPD=1
V
VRLC/VBIAS.
If CDACPD=0
V
[15:0]= D
[15:0]= 65535 − D
[15:0]=INT ( (
[15:0]=INT ( (
[15:0]=INT ( (
= V
V
V
RLC
RLC
V
V
3
RLC
CSTEP
CBOT
= V
1
is an externally applied voltage on pin
is the output from the internal RLC DAC.
V
+ (260mV x (DAC[7:0] − 127.5) ) / 127.5
= (
FS
: the minimum output of the RLC DAC
2
: the step size of the RLC DAC;
+ (0.66 + PGA[8:0] x 7.34 / 511)
: the ADC full-scale range
V
1
[15:0]
CSTEP
V
V
V
V
x CDAC[3:0] ) +
3
3
3
1
/
/
/
1
is added to the Offset DAC
V
V
V
V
[15:0]
FS
FS
FS
FS
= 2V / 1.2V)
) x 65535) + 32767
) x 65535) + 65535
) x 65535) + 0
November 24, 2011
HT82V46
V
CBOT