FXMA2104 FAIRCHILD [Fairchild Semiconductor], FXMA2104 Datasheet - Page 6

• Manufacturer Part Number: FXMA2104
• Description: Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2011 Fairchild Semiconductor Corporation
FXMA2104 • Rev. 1.0.1
Application Information
The FXMA2104 has open-drain I/Os and requires
external pull-up resistors on the eight data I/O pins, as
shown in Figure 3. If a pair of data I/O pins (A
used, both pins should be tied to GND (or both to V
In this case, pull-down or pull-up resistors are not
required. The recommended values for the pull-up
resistors (RPUs) are 1KΩ to 10K, depending on the total
bus capacitance, the user is free to vary the pull-up
resistor value to meet the maximum I
the I
For example, the maximum edge rate (30% - 70%)
during Fast Mode (400kbit/s) is 300ns. If bus
capacitance is approaching the maximum 400pF, lower
the RPU value to keep the rise time below 300ns (Fast
Mode). Section 7.1 of the I
excellent guideline for pull-up resistor sizing.
Theory of Operation
The FXMA2104 is designed for high-performance level
shifting and buffer / repeating in an I
Figure 1 shows that each bi-directional channel contains
two series-Npassgates and two dynamic drivers. This
hybrid architecture is highly beneficial in an I
application where auto-direction is a necessity.
For example, during the following three I
events:
the bus direction needs to change from master-to-slave
to slave-to-master without the occurrence of an edge. If
there is an I
in these examples, the I
direction when both A and B ports are LOW. The
Npassgates can accomplish this task very efficiently
because, when both A and B ports are LOW, the
Npassgates act as a low resistive short between the two
(A and B) ports.
Due to I
slaves are not push-pull drivers. Logic LOWs are “pulled
down” (I
example, when the master lets go of SCL (SCL always
comes from the master), the rise time of SCL is largely
determined by the RC time constant, where R = R
C = the bus capacitance. If the FXMA2104 is attached
to the master [on the A port] and there is a slave on the
B port, the Npassgates act as a low resistive short



2
C specification (UM10204 rev. 03, June 19, 2007).
Clock Stretching
Slave’s ACK Bit (9
Write Bit (8
Clock Synchronization and Multi Master
Arbitration
sink
2
C’s open-drain topology, I
), while logic HIGHs are “let go” (3-state). For
2
C translator between the master and slave
th
bit = 0)
th
bit = 0) following a Master’s
2
2
C translator must change
C specification provides an
2
2
C edge rate per
C masters and
2
C application.
2
C protocol
n
/B
n
) is not
PU
and
CC
2
C
).
6
between the ports until either of the port’s V
thresholds are reached. After the RC time constant has
reached the V
edge detector triggers both dynamic drivers to drive
their respective ports in the LOW-to-HIGH (LH)
direction, accelerating the rising edge. The resulting rise
time resembles the scope shot in Figure 4. Effectively,
two distinct slew rates appear in rise time. The first slew
rate (slower) is the RC time constant of the bus. The
second slew rate (much faster) is the dynamic driver
accelerating the edge.
If both the A and B ports of the translator are HIGH, a
high-impedance path exists between the A and B ports
because both the Npassgates are turned off. If a master
or slave device decides to pull SCL or SDA LOW, that
device’s driver pulls down (I
edge reaches the A or B port V
either the A or B port threshold is reached, the port’s
edge detector triggers both dynamic drivers to drive
their respective ports in the HIGH-to-LOW (HL)
direction, accelerating the falling edge.
Figure 4. Waveform C: 600pF, Total R
CC
/2 threshold of either port, the port’s
sink
) SCL or SDA until the
CC
/2 threshold. When
PU
www.fairchildsemi.com
: 2.2KΩ
CC
/2