ISPPAC30-01SI LATTICE [Lattice Semiconductor], ISPPAC30-01SI Datasheet - Page 28

• Manufacturer Part Number: ISPPAC30-01SI
• Description: In-System Programmable Analog Circuit
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this
instruction is defined by Lattice as shown in Table 6.
Figure 12. ID Code
ispPAC30 Specific Instructions
There are three unique address instructions specified by Lattice for the ispPAC30. They are ADDCFG (address
CFG), ADDCFGQ (address the CFG quick, or short register), and ADDUES (address the UES or user electronic
signature register). They all select their respective registers to be shifted into through TDI during a Shift-DR opera-
tion. Normal operation of a device is not interrupted by the execution of these instructions. They usually proceed a
program instruction (PROGCFG, or PROGUES) for putting the shifted data into E
(LATCHCFG) for putting data into the device control SRAM directly. The bit codes for these instructions are found in
Table 6.
There are three unique program instructions specified by Lattice for the ispPAC30. They are PROGUES (program
UES), PROGCFG (program CFG), and PROGESF (program the electronic security fuse bit). The first two store
their respective registers into E
simply sets the ESF bit so shifting out CFG information is no longer possible. The only way to recover the ability to
shift out meaningful data is to reset ESF by performing a CFGBE instruction. This, of course will reset the device
configuration as well, but will keep an unauthorized user from learning the bit pattern of the device. Normal opera-
tion of the device is not interrupted during the actual programming time. A programming operation does not begin
until entry of the Run-Test/Idle state. The programming time required to insure data retention is given in the timing
specifications. The user must ensure that the recommended programming times are observed to ensure specified
data retention. Note: When initially programming or reprogramming the ispPAC30 with software other than PAC-
Designer, or an authorized third-party programmer (e.g., via microcontroller), refer to the additional Lattice techni-
cal literature covering the required algorithms necessary for complete JTAG and SPI device programming control of
the ispPAC30 (specific bit assignments, word lengths, etc.).
There are two unique load instructions specified by Lattice for the ispPAC30. They are the LATCHCFG (load CFG
register) and RELOADCFG (load CFG from E
stored E
control SRAM, depending on whether the preceding address CFG was an ADDCFG or ADDCFGQ instruction. The
load operation does not occur until entry of the Run-Test/Idle state. Settling time for the new configuration will
depend on the configuration and time-constants of the particular circuit and can be anywhere from microseconds
to milliseconds. The actual switching to make the change, however, always occurs in less than a microsecond once
the Run-Test/Idle state is entered. The bit codes for these instructions are shown in Table 6.
There are two unique read instructions specified by Lattice for the ispPAC30. They are the READCFG (read CFG)
and READUES (read user electronic signature). These instructions read data out of the corresponding E
ration memory into either the CFG or UES register. This is done in preparation for either an ADDCFG or ADDUES
and then a subsequent shifting out of the data in these registers. Normal operation of a device is not interrupted by
the execution of these instructions. The bit code for these instructions are shown in Table 6.
The ENCAL (enable calibration) is a unique Lattice instruction that enables the start of an auto-calibration
sequence. This operation causes both output amplifiers to go to 0V until the calibration sequence is completed
2
configuration into the ispPAC30 device control SRAM. The LATCHCFG updates all or a portion of the
2
configuration memory. The third, PROGESF, has no register associated with it. It
MSB
E 2 Configured
XXXX / 0000 0001 0011 0000 / 0000 0100 001 / 1
Version
(4-bits)
0130h = PAC30
2
Part Number
). These instructions load the data in either the CFG register or the
(16-bits)
28
Lattice Semiconductor
JEDEC Manfacturer
Identity Code for
(11-bits)
per 1149.1-1990
Constant 1
ispPAC30 Preliminary Data Sheet
(1-bit)
LSB
2
configuration memory or a load
2
configu-