ISPPAC30-01SI LATTICE [Lattice Semiconductor], ISPPAC30-01SI Datasheet - Page 25

• Manufacturer Part Number: ISPPAC30-01SI
• Description: In-System Programmable Analog Circuit
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
ispPAC30 Preliminary Data Sheet
There are no boundary scan logic cells in the ispPAC30 architecture. This does not prevent the ispPAC30 from
functioning correctly, however, when placed in a valid serial chain with other IEEE 1149.1 compliant devices.
A brief description of the ispPAC30 JTAG interface follows. For complete details of the reference specification, refer
to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now
includes IEEE Std 1149.1a-1993). For complete documentation on how to use ispPAC30 in an embedded serial
interface control environment using the SPI protocol, please refer to application note AN6027, Using SPI to Config-
ure and Control the ispPAC30.
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the
ispPAC30. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct sequence,
instructions are shifted into an instruction register which then determines subsequent data input, data output, and
related operations. Device programming is performed by addressing the configuration register, shifting data in, and
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then executing a program configuration instruction, after which the data is transferred to internal E
CMOS cells. It is
these non-volatile cells that store the configuration or the ispPAC30. A separate set of SRAM registers are pre-
loaded at turn-on and determine the configuration of the ispPAC30 while it is under power. By cycling the TAP con-
troller through the necessary states, data can also be shifted out of the configuration register to verify the current
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ispPAC30 configuration in the control SRAM or of the stored E
configuration memory. Instructions exist to access
all data registers and perform other internal control operations.
For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification.
Others are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data reg-
isters defined by the manufacturer. The two required registers are the bypass and boundary-scan registers. For
ispPAC30, the bypass register is a 1-bit shift register that provides a short path through the device when boundary
testing or other operations are not being performed. The ispPAC30, as mentioned, has no boundary scan logic and
therefore no boundary scan register. All instructions relating to boundary scan operations place the ispPAC30 in
the BYPASS mode to maintain compliance with the specification. The optional identification register described in
IEEE 1149.1 is also included in the ispPAC30.
Two additional data registers are included in the TAP of the ispPAC30 are the Lattice defined CFG/CFGQ (configu-
ration and quick configuration) and UES (user electronic signature) registers. Figure 9 shows how the instruction
and various data registers are placed in an ispPAC30.
Figure 9. TAP Registers
E2 NON-VOLATILE MEMORY
SRAM DEVICE CONFIGURATION
CFG/CFGQ REGISTER (112/40 bits)
UES REGISTER (16 bits)
IDCODE REGISTER (32 bits)
BYPASS REGISTER (1 bit)
INSTRUCTION REGISTER (6 bits)
TEST ACCESS PORT
OUTPUT
(TAP) LOGIC
LATCH
TDO
TDI
TCK
TMS
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