ISPPAC30-01SI LATTICE [Lattice Semiconductor], ISPPAC30-01SI Datasheet - Page 24

• Manufacturer Part Number: ISPPAC30-01SI
• Description: In-System Programmable Analog Circuit
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
ispPAC30 Preliminary Data Sheet
In-System Programming
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The ispPAC30 is an in-system programmable device. This is accomplished by integrating all E
configuration mem-
ory and SRAM control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial
JTAG interface at normal logic levels. Once a device is programmed, all configuration information is stored on-chip,
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in non-volatile E
CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispPAC30 instruc-
tions are described in the JTAG interface section of this data sheet.
User Electronic Signature
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A user electronic signature (UES) feature is included in the E
CMOS memory of the ispPAC30. This consists of 16
bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control
data. The specifics this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispPAC30 device to prevent unauthorized readout of the
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E
CMOS configuration bit patterns. Once programmed, this cell prevents further access to the functional user bits
in the device. This cell can only be erased by reprogramming the device, so the original configuration can not be
examined once programmed. Usage of this feature is optional. The specifics of this feature are discussed in the
IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
Included in the basic ispPAC30 Design Kit is an engineering prototype board that can be connected to the parallel
port of a PC using a Lattice download cable. It demonstrates proper layout techniques for the ispPAC30 and can be
used in real time to check circuit operation as part of the design process. Input and output connections as well as a
“breadboard” circuit area are provided to speed debugging of the circuit. This board is also useful as a program-
ming fixture for prototype and short production runs.
Figure 8. Download to a PC
PAC-Designer
Software
Other
System
Circuitry
ispDownload
Cable (6')
4
ispPAC30
Device
IEEE Standard 1149.1 Interface
Serial Port Programming Interface Communication with the ispPAC30 is facilitated via an IEEE 1149.1 test access
port (TAP). It is used by the ispPAC30 as a serial programming interface, and not for boundary scan test purposes.
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