WM8980CGEFL/RV WOLFSON [Wolfson Microelectronics plc], WM8980CGEFL/RV Datasheet - Page 107

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WM8980CGEFL/RV

Manufacturer Part Number
WM8980CGEFL/RV
Description
Stereo CODEC with Speaker Driver and Video Buffer
Manufacturer
WOLFSON [Wolfson Microelectronics plc]
Datasheet
Pre-Production
w
44 (2Ch)
45 (2Dh)
REGISTER
ADDRESS
3:1
0
8
7
6
5
4
3
2
1
0
8
7
6
BIT
BEEPVOL
BEEPEN
MBVSEL
R2_2INP
PGA
RIN2INP
PGA
RIP2INP
PGA
L2_2INP
PGA
LIN2INP
PGA
LIP2INP
PGA
INPPGA
UPDATE
INPPGAZCL
INPPGA
MUTEL
LABEL
000
0
0
0
0
1
1
0
0
1
1
N/A
0
0
DEFAULT
AUXR input to ROUT2 inverter gain
000 = -15dB
...
111 = +6dB
0 = mute AUXR beep input
1 = enable AUXR beep input
Microphone Bias Voltage Control
0 = 0.9 * AVDD
1 = 0.6 * AVDD
Reserved
Connect R2 pin to right channel input PGA positive
terminal.
0=R2 not connected to input PGA
1=R2 connected to input PGA amplifier positive
terminal (constant input impedance).
Connect RIN pin to right channel input PGA
negative terminal.
0=RIN not connected to input PGA
1=RIN connected to right channel input PGA
amplifier negative terminal.
Connect RIP pin to right channel input PGA
amplifier positive terminal.
0 = RIP not connected to input PGA
1 = right channel input PGA amplifier positive
terminal connected to RIP (constant input
impedance)
Reserved
Connect L2 pin to left channel input PGA positive
terminal.
0=L2 not connected to input PGA
1=L2 connected to input PGA amplifier positive
terminal (constant input impedance).
Connect LIN pin to left channel input PGA negative
terminal.
0=LIN not connected to input PGA
1=LIN connected to input PGA amplifier negative
terminal.
Connect LIP pin to left channel input PGA amplifier
positive terminal.
0 = LIP not connected to input PGA
1 = input PGA amplifier positive terminal
connected to LIP (constant input impedance)
INPPGAVOLL and INPPGAVOLR volume do not
update until a 1 is written to INPPGAUPDATE (in
reg 45 or 46)
Left channel input PGA zero cross enable:
0=Update gain when gain register changes
1=Update gain on 1
write.
Mute control for left channel input PGA:
0=Input PGA not muted, normal operation
1=Input PGA muted (and disconnected from the
following input BOOST stage).
DESCRIPTION
st
zero cross after gain register
PP, Rev 3.8, May 2012
Analogue
Outputs
Analogue
Outputs
Input Signal
Path
Input Signal
Path
Input Signal
Path
Input Signal
Path
Input Signal
Path
Input Signal
Path
Input Signal
Path
Input Signal
Path
Input Signal
Path
Input Signal
Path
REFER TO
WM8980
107

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