71M6403-IGTR TERIDIAN [Teridian Semiconductor Corporation], 71M6403-IGTR Datasheet - Page 52

• Manufacturer Part Number: 71M6403-IGTR
• Description: Electronic Trip Unit
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

Many functions of the chip can be controlled via the I/O RAM (Configuration RAM). The CE will also take some of its parameters
from the I/O RAM.
Bits with a W (write) direction are written by the MPU into I/O RAM. Typically, they are initially stored in flash memory and copied
to the I/O RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The
remaining bits are mapped to 2xxx. Bits with R (read) direction can only be read by the MPU. On power up, all bits are cleared
to zero unless otherwise stated. Generic SFR registers are not listed.
Page: 52 of 75
Name
ADC_DIS
CE_EN
CHOP_EN[1:0]
RESERVED
COMP_INT[1:0]
COMP_STAT[2:0]
DIO_R0[2:0]
DIO_R1[2:0]
DIO_R2[2:0]
DIO_R3[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_DIR0[7:0]
DIO_DIR1[7:0]
DIO_DIR2[5:0]
Location
[Bit(s)]
2005[3]
2000[4]
2002[5:4]
2004[5]
2003[4:3]
2003[2:0]
2009[2:0]
2009[6:4]
200A[2:0]
200A[6:4]
200B[2:0]
200B[6:4]
200C[2:0]
200C[6:4]
200D[2:0]
200D[6:4]
200E[2:0]
200E[6:4]
SFR A2
SFR 91
SFR A1[5:0]
I/O RAM (Configuration RAM) – Alphabetical Order
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Dir
R
©
2006 TERIDIAN Semiconductor Corporation
Programs the direction of DIO pins 21 through 16. 1 indicates output.
Programs the direction of DIO pins 15 through 8. 1 indicates output.
Ignored if the pin is not configured as I/O.
Ignored if the pin is not configured as I/O.
Disables ADC and removes bias current
CE enable.
Chop enable for the reference band gap circuit.
Description
00: enabled 01: disabled 10: disabled 11: enabled
Must be 0.
Two bits establishing whether a comparator state change should
create MPU interrupts. 1: interrupt, 0: no interrupt. If 11, the
comparator outputs are XOR’ed.
Three bits containing comparator output status.
Connects dedicated I/O pins 0 to 11 to selectable internal resources. If
more than one input is connected to the same resource, the ‘Multiple’
column below specifies how they are combined. See Software User’s
Guide for details).
Programs the direction of DIO pins 7 through 0. 1 indicates output.
Ignored if the pin is not configured as I/O. See DIO_EEX for special
option for DIO4 and DIO5.
Bit0 = comp2, Bit1 = comp3
DIO_GP
0
1
2
3
4
5
6
7
Bit0 = comp1, Bit1 = comp2, Bit2 = comp3
High priority I/O interrupt (int0 falling)
High priority I/O interrupt (int0 rising)
Low priority I/O interrupt (int1 falling)
Low priority I/O interrupt (int1 rising)
T0 (counter0 clock)
T1 (counter1 clock)
Resource
Reserved
Electronic Trip Unit
NONE
71M6403
SEPTEMBER 2006
Multiple
OR
OR
OR
OR
OR
OR
OR
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REV 1.0