71M6403-IGTR TERIDIAN [Teridian Semiconductor Corporation], 71M6403-IGTR Datasheet - Page 33

• Manufacturer Part Number: 71M6403-IGTR
• Description: Electronic Trip Unit
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 45:
Each group of interrupt sources can be programmed individually to have one of four priority levels by setting or clearing one bit in
the special function register IP0 and one in IP1. If requests of the same priority level are received simultaneously, an internal
polling sequence as per Table 49 determines which request is serviced first.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by
the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). ZP8 has its own enable and flag
bits in addition to the interrupt 6 enable and flag bits (see Table 44). Note, the ZP8 interrupt must be cleared by the MPU
software.
Interrupt Priority 0 Register (IP0)
Interrupt Priority 1 Register (IP1)
Page: 33 of 75
Group
0
1
2
3
4
5
MSB
MSB
--
-
Serial channel 0 interrupt
External interrupt 0
External interrupt 1
WDTS
Timer 0 interrupt
Timer 1 interrupt
Note: WDTS is not used for interrupt control
-
IP1.x
-
0
0
1
1
IP0.5
IP1.5
Table 45: Priority Level Groups
©
Table 46: The IP0 Register:
Table 47: The IP1 Register:
2006 TERIDIAN Semiconductor Corporation
Table 48: Priority Levels
IP0.4
IP1.4
IP0.x
0
1
0
1
Serial channel 1 interrupt
IP0.3
IP1.3
Priority Level
Level0 (lowest)
Level1
Level2
Level3 (highest)
-
-
-
-
-
IP0.2
IP1.2
Electronic Trip Unit
IP0.1
IP1.1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
LSB
LSB
IP0.0
IP1.0
71M6403
SEPTEMBER 2006
REV 1.0