XR16C850CJ EXAR [Exar Corporation], XR16C850CJ Datasheet - Page 8

no-image

XR16C850CJ

Manufacturer Part Number
XR16C850CJ
Description
Manufacturer
EXAR [Exar Corporation]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR16C850CJ
Manufacturer:
ST
0
Part Number:
XR16C850CJ-F
Manufacturer:
Ericsson/INFINEON
Quantity:
350
Part Number:
XR16C850CJ-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR16C850CJ-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
SYMBOL DESCRIPTION
-LPT2/-DDIS
IRQB/-RXRDY
IRQC/-TXRDY
-LPT-1 /
-BAUDOUT
Symbol
XR16C850
Rev. 1.20
40
29
24
15
23
44
32
27
17
26
Pin
48
23
12
29
22
52
32
25
12
24
Signal
type
O
O
O
O
8
MCR bit-3 is set to a logic 1, interrupts are enabled
in the interrupt enable register (IER), and when an
interrupt condition exists. Interrupt conditions in-
clude: receiver errors, available receiver buffer data,
transmit buffer empty, or when a modem status flag
is detected. During STD mode operation the three
state mode is disabled and this pin functions as INT
(Interrupt Request).
Interrupt Request “B” or Receive Ready (three state,
dual function) -. During PC mode operation, a logic
1 indicates an interrupt IRQB (see further descrip-
tion under the IRQA). During the STD mode a logic
0 indicates receive data ready status, i.e. the RHR
is full or the FIFO has one or more RX characters
available for unloading. This pin goes to a logic 0
when the FIFO/RHR is full or when there are more
characters available in either the FIFO or RHR.
Interrupt Request “C” or Transmit Ready (three
state, dual function) - During PC mode operation, a
logic 1 on this pin indicates an interrupt IRQC (see
further description under the IRQA). During the STD
mode buffer ready status is indicated by a logic 0,
i.e., at least one location is empty and available in
the FIFO or THR. This pin goes to a logic 1 when
there are no more empty locations in the FIFO or
THR.
Baud Rate Generator Output or Line Printer Port-1
Decode Logic Output. (dual function, active low) -
When the PC mode is selected, the baud rate
generator clock output is internally connected to the
RCLK input. This pin then functions as the LPT-1
printer port decode logic output, see table 2. During
STD mode operation, this pin provides the 16X clock
of the selected data rate from the baud rate genera-
tor. The RCLK pin must be connected externally to
-BAUDOUT when the receiver is operating at the
same data rate.
Drive Disable or Line Printer Port-2 Decode Logic
Output (dual function, active low) - When the PC
Pin Description

Related parts for XR16C850CJ