XR16C850CJ EXAR [Exar Corporation], XR16C850CJ Datasheet - Page 13

• Manufacturer Part Number: XR16C850CJ
• Manufacturer: EXAR [Exar Corporation]

GENERAL DESCRIPTION
The XR16C850 provides serial asynchronous receive
data synchronization, parallel-to-serial and serial-to-
parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for
converting the serial data stream into parallel data that
is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding
start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integ-
rity is insured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for
any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially
when manufactured on a single integrated silicon chip.
The XR16C850 represents such an integration with
greatly enhanced features. The 850 is fabricated with
an advanced CMOS process.
The 850 is an upward solution that provides 128 bytes
of transmit and receive FIFO memory, instead of 32
bytes provided in the 16C650A, 16 bytes in the 16C550,
or none in the 16C450. The 850 is designed to work with
high speed modems and shared network environ-
ments, that require fast data processing time. In-
creased performance is realized in the 850 by the larger
transmit and receive FIFOs. This allows the external
processor to handle more networking tasks within a
given time. For example, the ST16C550 with a 16 byte
FIFO, unloads 16 bytes of receive data in 1.53 ms (This
example uses a character length of 11 bits, including
start/stop bits at 115.2Kbps). This means the external
CPU will have to service the receive FIFO at 1.53 ms
intervals. However with the 128 byte FIFO in the 850,
the data buffer will not require unloading/loading for 12.2
ms. This increases the service interval giving the
external CPU additional time for other applications and
reducing the overall UART interrupt servicing time. In
addition, the 4 selectable levels of FIFO trigger interrupt
and automatic hardware/software flow control is
uniquely provided for maximum data throughput perfor-
mance especially when operating in a multi-channel
environment. The combination of the above greatly
reduces the bandwidth requirement of the external
controlling CPU, increases performance, and reduces
power consumption.
Rev. 1.20
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The 850 provides a RS-485 half-duplex direction control
signal, pin –OP1/RS485, to select the external trans-
ceiver direction. It automatically changes the state of
the output pin after the last stop-bit of the last character
has been shifted out for receive state. Afterward, upon
loading a TX data byte it changes state of the output pin
back for transmit state. The RS-485 direction control
pin is not activated after reset. To activate the direction
control function, user has to set EFR Bit-4, and FCTR
Bit-3 to “1”. This pin is normally high for receive state,
low for transmit state.
Two data bus interfaces are available to the user. The
PC mode allows direct interconnect to the PC ISA bus
while the STD Mode operates similar to the standard
CPU interface available on the 16C450/550/650A.
When the PC mode is selected, the external logic
circuitry required for PC COM port address decode and
chip select is eliminated. These functions are provided
internally in the 850.
The 850 is capable of operation to 1.5Mbps with a 24
MHz crystal or external clock input. With a crystal of
14.7464 MHz and through a software option, the user
can select data rates up to 460.8Kbps or 921.6Kbps.
The rich feature set of the 850 is available through
internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger
levels, selectable TX and RX baud rates, infrared en-
coder/decoder interface, modem interface controls,
and a sleep mode are all standard features. In addition
the 44/48/52 pin packages offer the PC Mode, two
additional three state interrupt lines and one selectable
open source interrupt output. The open source interrupt
scheme allows multiple interrupts to be combined in a
“WIRE-OR” operation, thus reducing the number of
interrupt lines in larger systems. Following a power on
reset or an external reset, the 850 is software compat-
ible with previous generation of UARTs, 16C450,
16C550 and 16C650A.
XR16C850