XR16C850CJ EXAR [Exar Corporation], XR16C850CJ Datasheet - Page 30

• Manufacturer Part Number: XR16C850CJ
• Manufacturer: EXAR [Exar Corporation]

ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared is the default condition)
These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (See Interrupt Source
Table).
ISR BIT 4-5: (logic 0 or cleared is the default condition)
These bits are enabled when EFR bit-4 is set to a logic
1. ISR bit-4 indicates that matching Xoff character(s)
have been detected. ISR bit-5 indicates that CTS, RTS
have been generated. Note that once set to a logic 1, the
ISR bit-4 will stay a logic 1 until Xon character(s) are
received.
ISR BIT 6-7: (logic 0 or cleared is the default condition)
These bits are set to a logic 0 when the FIFO is not being
used. They are set to a logic 1 when the FIFOs are
enabled
Line Control Register (LCR)
The Line Control Register is used to specify the asyn-
chronous data communication format. The word length,
the number of stop bits, and the parity are selected by
writing the appropriate bits in this register. This register
also has a secondary function to select 2 other register
Priority
Level
XR16C850
1
2
2
3
4
5
6
Table 6, INTERRUPT SOURCE TABLE
Rev. 1.20
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
[ ISR BITS ]
0
0
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
30
Source of the interrupt
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xoff signal)/ Special character
CTS, RTS change of state
sets. The first is by setting bit-7 = 1 to select the baud
rate divisor (DLL and DLM) registers, and the second set
of registers is selected when a “BF” hex is written to LCR
to select the enhanced register set.
LCR BIT 0-1: (logic 0 or cleared is the default condition)
These two bits specify the word length to be transmitted
or received. The upper unused bit(s) in the received data
byte is set to zero.
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in conjunc-
tion with the programmed word length.
BIT-1
BIT-2
0
0
1
1
0
1
1
BIT-0
Word length
0
1
0
1
5,6,7,8
6,7,8
5
Word length
(Bit time(s))
5
6
7
8
Stop bit
length
1-1/2
1
2