XR16C850CJ EXAR [Exar Corporation], XR16C850CJ Datasheet
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XR16C850CJ
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XR16C850CJ Summary of contents
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... June 1999-1 PLCC Package XR16C850CJ 34 "STD" MODE CONNECTION XR16C850CJ "PC" MODE 34 CONNECTION Pins Package Operating Temperature 40 PDIP -40° 85° PLCC -40° 85° TQFP -40° 85° QFP -40° ...
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XR16C850 D11 RCLK XR16C850CM CS0 CS1 -CS2 -LPT1 / -BAUDOUT ...
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D0-D7 -IOR,IOR -IOW,IOW RESET A0-A2 -AS CS0,CS1 -CS2 -DDIS INT -RXRDY -TXRDY XTAL1 RCLK XTAL2 -BAUDOUT Figure 2. BLOCK DIAGRAM (STANDARD MODE) Rev. 1.20 XR16C850 Transmit Transmit FIFO Shift Registers Register Flow Ir Control Encoder Logic Receive Receive FIFO Shift ...
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XR16C850 D0-D7 -IOR -IOW A0-A9 -AEN S1, S2,S3 -LPT1 -LPT2 IRQA IRQB IRQC GND Rev. 1.20 Transmit FIFO Registers Flow Control Logic Receive FIFO Registers Flow Control Logic Clock & Baud Rate Generator Figure 3. BLOCK DIAGRAM (PC MODE) 4 ...
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SYMBOL DESCRIPTION Symbol Pin IOR CS0 CS1 -CS2 14 16 Rev. 1.20 ...
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XR16C850 SYMBOL DESCRIPTION Symbol Pin IOW -AEN / - -BAUDOUT D0-D7 1-8 2-9 43-47 D10, D11 D12 Rev. 1.20 Signal 48 52 type to GND when CS0 ...
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SYMBOL DESCRIPTION Symbol Pin 40 44 BUS8/ CLK8/ DRQ - - -DACK - - -DDIS GND 20 22 INT -IOR 21 24 -IOW 18 20 IRQA / INT 30 33 Rev. 1.20 Signal 48 52 type ...
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XR16C850 SYMBOL DESCRIPTION Symbol Pin 40 44 IRQB/-RXRDY 29 32 IRQC/-TXRDY 24 27 -LPT-1 / -BAUDOUT 15 17 -LPT2/-DDIS 23 26 Rev. 1.20 Signal 48 52 type MCR bit-3 is set to a logic 1, interrupts are enabled in the ...
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SYMBOL DESCRIPTION Symbol Pin 40 44 -OP1/RS485 34 38 -OP2 RCLK RESET 35 39 -RXRDY RCLK 9 10 Rev. 1.20 Signal 48 52 type mode is selected, this pin functions as the LPT-2 printer port ...
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XR16C850 SYMBOL DESCRIPTION Symbol Pin -OP2 31 35 SEL - -TXRDY VCC 40 44 XTAL1 16 18 XTAL2 -CTS 36 40 Rev. 1.20 Signal 48 52 type ...
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SYMBOL DESCRIPTION Symbol Pin 40 44 -DSR 37 41 -DTR -RTS IRRX 10 11 Rev. 1.20 Signal 48 52 type reading MSR bit-4. This pin only affects the transmit and receive ...
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XR16C850 SYMBOL DESCRIPTION Symbol Pin IRTX 11 13 CLKSEL - - -DMA - - Rev. 1.20 Signal 48 52 type or “mark” condition). The inactive state (no data) for the Infrared decoder interface is a logic ...
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GENERAL DESCRIPTION The XR16C850 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to- parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with ...
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XR16C850 FUNCTIONAL DESCRIPTIONS Interface Options Standard 16550 Mode Interface The 850 provides a pin compatible interface for emula- tion of the 16C550 when in the STD mode. The STD mode is selected by making the SEL pin a logic 1 ...
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PC Mode Interface (available on 44/48/52 pin ver- sions only) The PC mode is selected by making the SEL pin a logic 0 (GND). When the PC mode is selected, the 850 eliminates the external address decode logic circuitry that ...
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XR16C850 SEL Table 2. PC MODE INTERNAL ADDRESS DECODE FUNCTIONS Note *2: All interrupt outputs are inactive ...
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Internal Registers The 850 provides 15 internal registers for monitoring and control. These registers are shown in Table 3 below. Twelve registers are similar to those already available in the standard 16C550. These registers function as data holding registers (THR/RHR), ...
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XR16C850 FIFO Operation The 128 byte transmit and receive data FIFO’s are enabled by the FIFO Control Register (FCR) bit-0. With 16C550 devices, the user can only set the receive trigger level but not the transmit trigger level. The 850 ...
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Software Flow Control When software flow control is enabled, the 850 com- pares one or two sequential receive data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed val- ues, the 850 will ...
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XR16C850 (Programmed word length) + 12. To convert the time out value to a character value, the user has to consider the complete word length, including data information length, start bit, parity bit, and the size of stop bit, i.e., ...
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Output Output Baud Rate Baud Rate 16 x Clock MCR MCR Divisor BIT-7=1 Bit-7=0 (Decimal) 50 200 75 300 150 600 300 1200 600 2400 1200 4800 2400 9600 4800 19.2K 7200 28.8K 9600 38.4k 19.2k 76.8k 38.4k 153.6k 57.6k ...
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XR16C850 DMA Operation The 850 FIFO trigger level provides additional flexibility to the user for block transfer operation. LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the ...
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D0-D7 -IOR,IOR -IOW,IOW RESET A0-A2 -AS CS0,CS1 -CS2 -DDIS INT -RXRDY -TXRDY XTAL1 RCLK XTAL2 -BAUDOUT Figure 12. INTERNAL LOOPBACK MODE DIAGRAM Rev. 1.20 XR16C850 Transmit Transmit FIFO Shift Registers Register Flow Ir Control Encoder Logic Receive Receive FIFO Shift ...
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XR16C850 REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the fifteen 850 internal registers. The assigned bit functions are more fully defined in the following paragraphs. XR16C850 ACCESSIBLE REGISTERS Register BIT-7 [Default] Note ...
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Register BIT-7 [Default] Note *3 Enhanced Registers are accessible only when LCR is set to "BF" Hex Xon-1[00] bit Xon-2[00] bit- Xoff-1[00] bit Xoff-2[00] bit-15 ...
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XR16C850 Transmit and Receive Holding Register The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Reg- ister (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the ...
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Logic 1 = Enable the receiver ready interrupt. The receiver ready interrupt is cleared when LSR is read. IER BIT-1: Logic 0 = Disable the transmitter empty interrupt. (normal default condition) Logic 1 = Enable the transmitter empty interrupt. The ...
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XR16C850 FCR BIT-2: Logic FIFO transmit reset. (normal default condition) Logic 1 = Clears the FIFO counter and resets the pointers logic (the transmit shift register is not cleared or altered). This bit will return to a ...
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TRIGGER TABLE-A (Receive) “Default setting after reset, ST16C550 mode” BIT-7 BIT-6 FIFO trigger level TRIGGER TABLE-B (Receive) BIT-7 BIT-6 FIFO trigger level ...
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XR16C850 Table 6, INTERRUPT SOURCE TABLE Priority [ ISR BITS ] Level Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit ...
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LCR BIT-3: Parity or no parity can be selected via this bit. Logic parity (normal default condition) Logic parity bit is generated during the transmis- sion, the receiver checks and reports parity error in ...
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XR16C850 MCR BIT-6: Logic 0 = Enable Modem receive and transmit input/ output interface. (normal default condition) Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/ Inputs are routed to the infrared ...
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Logic least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when LSR register is read. Modem Status Register (MSR) This register provides the current state of the ...
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XR16C850 Cont-3 Cont-2 Cont Table 7. SOFTWARE ...
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EFR bit-7: Automatic CTS Flow Control. Logic 0 = Automatic CTS flow control is disabled. (normal default condition) Logic 1 = Enable Automatic CTS flow control. Transmis- sion will stop when -CTS goes to a logical 1. Transmis- sion will ...
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XR16C850 ENHANCED MODE SELECT REGISTER (EMSR) This register is accessible only when FCTR Bit-6 is set to “1”. EMSR BIT-0: “Write only” Receive FIFO count register. The scratch pad register is used to provide the receive FIFO count ...
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AC ELECTRICAL CHARACTERISTICS T =0° - 70° -40° - +85° C for IP, IJ, IQ packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter T ,T Clock pulse duration Oscillator/Clock frequency ...
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XR16C850 ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation DC ELECTRICAL CHARACTERISTICS T =0° - 70° -40° - +85° C for IP, IJ, IQ packages), Vcc=3.3 - 5.0 V ± 10% ...
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T2w EXTERNAL CLOCK -BAUDOUT 1/2 -BAUDOUT 1/3 -BAUDOUT 1/3> -BAUDOUT Rev. 1.20 T1w T3w Clock Timing 39 XR16C850 X450-CK-1 ...
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XR16C850 T4w -AS T5s A0-A2 Address T6s -CS2 CS1-CS0 T7d T8d -IOR IOR T11d -DDIS T12d D0-D7 General Read timing in "STD mode" Rev. 1.20 T5h Valid T6h Valid T7h T7w T9d Active T11d Active T12h Data 40 X550-RD-1 ...
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T4w -AS T5s A0-A2 Address T6s -CS2 CS1-CS0 T13d T14d -IOW IOW D0-D7 Rev. 1.20 T5h Valid T6h Valid T13h T13w T15d Active T16s T16h Data General Write timing in "STD mode" 41 XR16C850 X550-WD-1 ...
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XR16C850 A0-A9 Address T6s -AEN T7d -IOR T12s D0-D7 A0-A9 Address T6s -AEN T13d -IOW D0-D7 Rev. 1.20 Valid Active T7w T7d T9d Active T12h Data General Read timing in "PC mode" Valid Active T13h T13w T15d Active T16s T16h ...
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Active IOW -RTS Change of state -DTR -CD -CTS -DSR INT -IOR IOR -RI Rev. 1.20 T17d Change of state Change of state T18d Active T19d Active Modem Input/Output timing 43 XR16C850 Change of state T18d Active Active Active ...
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XR16C850 START BIT RX INT -IOR IOR Rev. 1.20 DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Receive timing 44 STOP BIT D6 D7 PARITY NEXT ...
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START BIT RX -RXRDY -IOR IOR Receive Ready timing in non FIFO mode Rev. 1.20 DATA BITS (5- XR16C850 STOP BIT D6 D7 PARITY NEXT BIT DATA START BIT T25d Active Data Ready ...
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XR16C850 START BIT RX -RXRDY -IOR IOR Receive Ready timing in FIFO mode Rev. 1.20 DATA BITS (5- STOP BIT D6 D7 PARITY First byte BIT that reaches the trigger level T25d Active ...
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START BIT TX INT -IOW Active IOW Rev. 1.20 DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS T23d 16 BAUD RATE CLOCK Transmit timing 47 XR16C850 STOP BIT ...
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XR16C850 START BIT TX -IOW IOW BYTE #128 -TXRDY Transmit Ready timing in non FIFO mode Rev. 1.20 DATA BITS (5- T27d 48 STOP BIT D6 D7 PARITY NEXT BIT DATA START BIT T28d ...
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START BIT TX -IOW Active IOW D0-D7 BYTE #128 T27d -TXRDY Transmit Ready timing in FIFO mode Rev. 1.20 DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS T28d FIFO Full ...
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XR16C850 IRTX Bit Time IRRX Bit Time Rev. 1.20 UART Frame Data Bits 3/16 Bit Time Infrared transmit timing Data Bits UART ...
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Rev. 1.20 XR16C850 51 ...
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XR16C850 Rev. 1.20 52 ...
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Rev. 1.20 XR16C850 53 ...
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XR16C850 Rev. 1.20 54 ...
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EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under ...