SX18AA100-I/DP ETC [List of Unclassifed Manufacturers], SX18AA100-I/DP Datasheet - Page 7

• Manufacturer Part Number: SX18AA100-I/DP
• Description: Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug
• Manufacturer: ETC [List of Unclassifed Manufacturers]

3.0 PORT DESCRIPTIONS
The device contains a 4-bit I/O port (Port A) and two 8-bit
I/O ports (Port B, Port C). Port A provides symmetrical
drive capability. Each port has three associated 8-bit reg-
isters (Direction, Data, TTL/CMOS Select, and Pull-Up
Enable) to configure each port pin as Hi-Z input or output,
to select TTL or CMOS voltage levels, and to enable/dis-
able the weak pull-up resistor. The upper four bits of the
registers associated with Port A are not used. The least
significant bit of the registers corresponds to the least
significant port pin. To access these registers, an appro-
priate value must be written into the MODE register.
Upon power-up, all bits in these registers are initialized to
“1”.
3.1 Reading and Writing the Ports
The three ports are memory-mapped into the data mem-
ory address space. To the CPU, the three ports are avail-
able as the RA, RB, and RC file registers at data memory
addresses 05h, 06h, and 07h, respectively.
© 2000 Scenix Semiconductor, Inc. All rights reserved.
WR
WR
WR
WR
0 = Pullup Enable
1 = Pullup Disable
RD
0 = CMOS
1 = TTL
0 = Output
1 = Hi-Z Input
RA Data
Figure 3-1. Port A Configuration
PLP_A
LVL_A
Direction
RA
Port A INPUT
- 7 -
The associated registers allow for each port bit to be indi-
vidually configured under software control as shown
below:
Writing to a port data register sets the voltage levels of
the corresponding port pins that have been configured to
operate as outputs. Reading from a register reads the
voltage levels of the corresponding port pins that have
been configured as inputs.
MODE
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
Data Direction
Registers:
RA, RB, RC
Output
0
M
U
X
CMOS Buffer
TTL Buffer
Input
Hi-Z
Table 3-1. Port Configuration
1
V
TTL/CMOS
Select Registers:
LVL_A, LVL_B,
LVL_C
CMOS
dd
Port A PIN
0
Pullup
TTL
1
Pullup Enable
Registers:
PLP_A, PLP_B,
PLP_C
Enable
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0
Disable
1