SX18AA100-I/DP ETC [List of Unclassifed Manufacturers], SX18AA100-I/DP Datasheet - Page 36

• Manufacturer Part Number: SX18AA100-I/DP
• Description: Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug
• Manufacturer: ETC [List of Unclassifed Manufacturers]

Bitwise Operations
CLRB fr.bit
SB fr.bit
SETB fr.bit
SNB fr.bit
Data Movement Instructions
MOV fr,W
MOV W,fr
MOV W,fr-W
MOV W,#lit
MOV W,/fr
MOV W,--fr
MOV W,++fr
MOV W,<<fr
MOV W,>>fr
MOV W,<>fr
MOV W,M
MOVSZ W,--fr
MOVSZ W,++fr
MOV M,W
MOV M,#lit
MOV !rx,W
MOV !OPTION, W Move W to OPTION Register (OPTION = W)
TEST fr
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
© 2000 Scenix Semiconductor, Inc. All rights reserved.
Mnemonic,
Operands
Clear Bit in fr (fr.bit = 0)
Test Bit in fr and Skip if Set (test fr.bit and skip
next instruction if bit is 1)
Set Bit in fr (fr.bit = 1)
Test Bit in fr and Skip if Clear (test fr.bit and skip
next instruction if bit is 0)
Move W to fr (fr = W)
Move fr to W (W = fr)
Move (fr-W) to W (W = fr - W); complement of
carry bit is subtracted if CF bit in FUSEX register
is cleared to 0
Move Literal to W (W = lit)
Move Complement of fr to W (W = fr ^ FFh)
Move (fr-1) to W (W = fr - 1)
Move (fr+1) to W (W = fr + 1)
Rotate fr Left through Carry and Move to W
(W = << fr)
Rotate fr Right through Carry and Move to W
(W = >> fr)
Swap High/Low Nibbles of fr and move to W
(W = <> fr)
Move MODE Register to W (W = MODE), high
nibble is cleared
Move (fr-1) to W and Skip if Zero (W = fr -1 and
skip next instruction if result is zero)
Move (fr+1) to W and Skip if Zero (W = fr + 1 and
skip next instruction if result is zero)
Move W to MODE Register (MODE = W)
Move Literal to MODE Register (MODE = lit)
Move W to Port Rx Control Register:rx <=> W
(exchange W and WKPND_B or CMP_B) or rx
= W (move W to rx for all other port control reg-
isters)
Test fr for Zero (fr = fr to set or clear Z bit)
Table 16-1. The SX Instruction Set (Continued)
Description
- 36 -
(Compatible)
Cycles
2 (skip)
2 (skip)
2 (skip)
2 (skip)
1 or
1 or
1 or
1 or
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(Turbo)
Cycles
2 (skip)
2 (skip)
2 (skip)
2 (skip)
1 or
1 or
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000 001f ffff
0010 000f ffff
0000 100f ffff
1100 kkkk kkkk
0010 010f ffff
0000 110f ffff
0010 100f ffff
0011 010f ffff
0011 000f ffff
0011 100f ffff
0000 0100 0010
0010 110f ffff
0011 110f ffff
0000 0100 0011
0000 0101 kkkk
0000 0000 0fff
0000 0000 0010
0010 001f ffff
0100 bbbf ffff
0111 bbbf ffff
0101 bbbf ffff
0110 bbbf ffff
Opcode
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Affected
C, DC, Z
none
none
none
none
none
none
none
none
none
none
none
none
none
none
Bits
C
C
Z
Z
Z
Z
Z