SX18AA100-I/DP ETC [List of Unclassifed Manufacturers], SX18AA100-I/DP Datasheet - Page 19

• Manufacturer Part Number: SX18AA100-I/DP
• Description: Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug
• Manufacturer: ETC [List of Unclassifed Manufacturers]

8.0 INTERRUPT SUPPORT
The device supports both internal and external maskable
interrupts. The internal interrupt is generated as a result
of the RTCC rolling over from 0FFh to 00h. This interrupt
source has an associated enable bit located in the
OPTION register. There is no pending bit associated with
this interrupt.
Port B provides the source for eight external software
selectable, edge sensitive interrupts. These interrupt
sources share logic with the Multi-Input Wakeup circuitry.
The WKEN_B register allows interrupt from Port B to be
individually enabled or disabled. Clearing a bit in the
WKEN_B register enables the interrupt on the corre-
sponding Port B pin. The WKED_B selects the transition
© 2000 Scenix Semiconductor, Inc. All rights reserved.
WKPND_B
WKED_B
STATUS
Register
PD bit
1 = Ext. Interrupt through Port B
0 = Power Down Mode, no Ext. Interrupt
From MODE
(MODE = 0A)
WKPND_B
WKED_B
From MODE
(MODE = 09)
Figure 8-1. Interrupt Structure
OPTION
RTE_IE
WKEN_B
- 19 -
RTCC
edge to be either positive or negative. The WKEN_B and
WKED_B registers are set to FFh upon reset. Setting a
bit in the WKED_B register selects the falling edge while
clearing the bit selects the rising edge on the correspond-
ing Port B pin.
The WKPND_B register serves as the external interrupt
pending register.
The WKPND_B register comes up a with random value
upon reset. The user program must clear the WKPND_B
register prior to enabling the interrupt. The proper
sequence is described in Section 7.2 .
Figure 8-1 shows the structure of the interrupt logic.
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
Overflow
Port B PIN
000
PC
Interrupt
Interrupt Stack
PC
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