SX18AA100-I/DP ETC [List of Unclassifed Manufacturers], SX18AA100-I/DP Datasheet - Page 35

• Manufacturer Part Number: SX18AA100-I/DP
• Description: Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug
• Manufacturer: ETC [List of Unclassifed Manufacturers]

Logical Operations
AND fr, W
AND W, fr
AND W,#lit
NOT fr
OR fr,W
OR W,fr
OR W,#lit
XOR fr,W
XOR W,fr
XOR W,#lit
Arithmetic and Shift Operations
ADD fr,W
ADD W,fr
CLR fr
CLR W
CLR !WDT
DEC fr
DECSZ fr
INC fr
INCSZ fr
RL fr
RR fr
SUB fr,W
SWAP fr
16.0 INSTRUCTION SET SUMMARY TABLE
Table 16-1 lists all of the instructions, organized by cate-
gory. For each instruction, the table shows the instruction
mnemonic (as written in assembly language), a brief
description of what the instruction does, the number of
instruction cycles required for execution, the binary
opcode, and the status bits affected by the instruction.
The “Cycles” column typically shows a value of 1, which
means that the overall throughput for the instruction is
one per clock cycle. In some cases, the exact number of
© 2000 Scenix Semiconductor, Inc. All rights reserved.
Mnemonic,
Operands
AND of fr and W into fr (fr = fr & W)
AND of W and fr into W (W = W & fr)
AND of W and Literal into W (W = W & lit)
Complement of fr into fr (fr = fr ^ FFh)
OR of fr and W into fr (fr = fr | W)
OR of W and fr into fr (W = W | fr)
OR of W and Literal into W (W = W | lit)
XOR of fr and W into fr (fr = fr ^ W)
XOR of W and fr into W (W = W ^ fr)
XOR of W and Literal into W (W = W ^ lit)
Add W to fr (fr = fr + W); carry bit is added if CF
bit in FUSEX register is cleared to 0
Add fr to W (W = W + fr); carry bit is added if CF
bit in FUSEX register is cleared to 0
Clear fr (fr = 0)
Clear W (W = 0)
Clear Watchdog Timer, clear prescaler if as-
signed to the Watchdog (TO = 1, PD = 1)
Decrement fr (fr = fr - 1)
Decrement fr and Skip if Zero (fr = fr - 1 and skip
next instruction if result is zero)
Increment fr (fr = fr + 1)
Increment fr and Skip if Zero (fr = fr + 1 and skip
next instruction if result is zero)
Rotate fr Left through Carry (fr = << fr)
Rotate fr Right through Carry (fr = >> fr)
Subtract W from fr (fr = fr - W); complement of
the carry bit is subtracted if CF bit in FUSEX
register is cleared to 0
Swap High/Low Nibbles of fr (fr = <> fr)
Description
Table 16-1. The SX Instruction Set
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cycles depends on the outcome of the instruction (such
as the test-and-skip instructions) or the clocking mode
(Compatible or Turbo). In those cases, all possible num-
bers of cycles are shown in the table.
The instruction execution time is derived by dividing the
oscillator frequency by either one (Turbo mode) or four
(Compatible mode). The divide-by factor is selected
through the FUSE Word register.
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
(Compatible)
Cycles
2 (skip)
2 (skip)
1 or
1 or
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(Turbo)
Cycles
2 (skip)
2 (skip)
1 or
1 or
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0001 111f ffff
0001 110f ffff
0000 011f ffff
0000 0100 0000
0000 0000 0100
0000 111f ffff
0010 111f ffff
0010 101f ffff
0011 111f ffff
0011 011f ffff
0011 001f ffff
0000 101f ffff
0011 101f ffff
0001 011f ffff
0001 010f ffff
1110 kkkk kkkk
0010 011f ffff
0001 001f ffff
0001 000f ffff
1101 kkkk kkkk
0001 101f ffff
0001 100f ffff
1111 kkkk kkkk
Opcode
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Affected
C, DC, Z
C, DC, Z
C, DC, Z
TO, PD
none
none
none
Bits
C
C
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z