TMS470R1B512 AD [Analog Devices], TMS470R1B512 Datasheet - Page 39

• Manufacturer Part Number: TMS470R1B512
• Description: 16/32-Bit RISC Flash Microcontroller
• Manufacturer: AD [Analog Devices]

SCIn ISOSYNCHRONOUS MODE TIMINGS INTERNAL CLOCK
Timing Requirements for Internal Clock SCIn Isosynchronous Mode
(see
(1) BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
(2) t
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
t
t
t
t
t
t
t
c(SCC)
w(SCCL)
w(SCCH)
d(SCCH-TXV)
v(TX)
su(RX-SCCL)
v(SCCL-RX)
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Figure
c(ICLK)
A.
Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the
SCICLK falling edge.
= interface clock cycle time = 1/f
16)
Cycle time,
SCInCLK
Pulse duration,
SCInCLK low
Pulse duration,
SCInCLK high
Delay time,
SCInCLK high to
SCInTX valid
Valid time,
SCInTX data
after SCInCLK
low
Setup time,
SCInRX before
SCInCLK low
Valid time,
SCInRX data
after SCInCLK
low
SCICLK
SCIRX
SCITX
Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
–t
t
c(ICLK)
0.5t
0.5t
c(ICLK)
t
c(SCC)
2t
c(SCC)
c(SCC)
IS EVEN OR BAUD = 0
MIN
c(ICLK)
+ t
+ t
(ICLK)
– 10
f
f
+ 20
– t
– t
+ 20
(BAUD + 1)
f
r
t
w(SCCL)
t
d(SCCH TXV)
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0.5t
0.5t
2
24
c(SCC)
c(SCC)
t
MAX
c(SCC)
t
10
c(ICLK)
+ 5
+ 5
t
w(SCCH)
t
su(RX SCCL)
0.5t
0.5t
c(SCC)
c(SCC)
–t
t
c(ICLK)
c(ICLK)
Data Valid
t
c(SCC)
3t
16/32-Bit RISC Flash Microcontroller
+ 0.5t
- 0.5t
Data Valid
MIN
c(ICLK)
+ t
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
+ t
t
– 10
v(TX)
f
f
c(ICLK)
IS ODD AND BAUD
c(ICLK)
+ 20
+ 20
(BAUD + 1)
– t
– t
(1) (2) (3)
r
f
0.5t
0.5t
t
v(SCCL RX)
(2
c(SCC)
c(SCC)
24
0
– 1) t
MAX
TMS470R1B512
10
+ 0.5t
– 0.5t
c(ICLK)
c(ICLK)
c(ICLK)
UNI
ns
ns
ns
ns
ns
ns
ns
T
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