TMS470R1B512 AD [Analog Devices], TMS470R1B512 Datasheet - Page 35

• Manufacturer Part Number: TMS470R1B512
• Description: 16/32-Bit RISC Flash Microcontroller
• Manufacturer: AD [Analog Devices]

SPIn Master Mode External Timing Parameters
(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)
(1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
(2) t
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4) When the SPI is in master mode, the following must be true:
(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
NO.
2
3
4
5
6
7
1
(5)
(5)
(5)
(5)
(6)
(6)
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For PS values from 1 to 255: t
For PS values of 0: t
c(ICLK)
t
t
t
t
t
t
t
t
t
t
t
t
t
c(SPC)M
w(SPCH)M
w(SPCL)M
w(SPCL)M
w(SPCH)M
v(SIMO-SPCH)M
v(SIMO-SPCL)M
v(SPCH-SIMO)M
v(SPCL-SIMO)M
su(SOMI-SPCH)M
su(SOMI-SPCL)M
v(SPCH-SOMI)M
v(SPCL-SOMI)M
(clock polarity = 0)
(clock polarity = 1)
= interface clock cycle time = 1/f
SPInSIMO
SPInSOMI
SPInCLK
SPInCLK
Cycle time, SPInCLK
Pulse duration, SPInCLK high (clock polarity = 0)
Pulse duration, SPInCLK low (clock polarity = 1)
Pulse duration, SPInCLK low (clock polarity = 0)
Pulse duration, SPInCLK high (clock polarity = 1)
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0)
Valid time, SPInCLK low after SPInSIMO data valid
(clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
Setup time, SPInSOMI before SPInCLK high (clock polarity = 0)
Setup time, SPInSOMI before SPInCLK low (clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
c(SPC)M
Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 1)
= 2t
c(SPC)M
c(ICLK)
(ICLK)
(PS +1)t
100 ns.
(4)
c(ICLK)
Submit Documentation Feedback
Master Out Data Is Valid
100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
Master In Data
Must Be Valid
4
6
5
2
16/32-Bit RISC Flash Microcontroller
7
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
1
(1) (2) (3)
0.5t
0.5t
0.5t
0.5t
0.5t
0.5t
0.5t
0.5t
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
(see
MIN
100
6
6
4
4
3
– 5 – t
– 5 – t
Figure
– 15
– 15
– t
– t
– t
– t
r
f
f
r
r
f
Data Valid
TMS470R1B512
13)
0.5t
0.5t
0.5t
0.5t
256t
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
MAX
c(ICLK)
+ 5
+ 5
+ 5
+ 5
UNIT
ns
ns
ns
ns
ns
ns
ns
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