TMS470R1B512 AD [Analog Devices], TMS470R1B512 Datasheet - Page 14

• Manufacturer Part Number: TMS470R1B512
• Description: 16/32-Bit RISC Flash Microcontroller
• Manufacturer: AD [Analog Devices]

TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
14
Flash Read
The B512 flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to
0xFFE0_0000. The flash is addressed through memory selects 0 and 1.
Flash Pipeline Mode
When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz. In normal mode, the
flash operates with a system clock frequency in normal mode of up to 24 MHz. Flash in pipeline mode is capable
of accessing 64-bit words and provides two 32-bit pipelined words to the CPU. Also in pipeline mode, the flash
can be read with no wait states when memory addresses are contiguous (after the initial 1-or 2-wait-state reads).
Flash Program and Erase
The B512 device flash contains two 256K-byte memory arrays (or banks) for a total of 512K bytes of flash and
consists of fourteen sectors. These fourteen sectors are sized as follows:
The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit
word.
For more detailed information on flash program and erase operations, see the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).
SECTOR NO.
0
1
2
3
4
5
6
7
8
9
0
1
2
3
The flash external pump voltage (V
and read).
After a system reset, pipeline mode is disabled (FMREGOPT[0] = 0). In other words,
the B512 device powers up and comes out of reset in non-pipeline mode.
Furthermore, setting the flash configuration mode bit (GBLCTRL[4]) will override
pipeline mode.
The flash external pump voltage (V
and read).
SEGMENT
16K Bytes
16K Bytes
32K Bytes
32K Bytes
32K Bytes
32K Bytes
32K Bytes
32K Bytes
16K Bytes
16K Bytes
64K Bytes
64K Bytes
64K Bytes
64K Bytes
Table 4. B512 Flash Memory Banks and Sectors
LOW ADDRESS
0x0003C000
0x00000000
0x00004000
0x00008000
0x00010000
0x00018000
0x00020000
0x00028000
0x00030000
0x00038000
0x00040000
0x00050000
0x00060000
0x00070000
Submit Documentation Feedback
CCP
CCP
) is required for all operations (program, erase,
) is required for all operations (program, erase,
NOTE:
NOTE:
NOTE:
HIGH ADDRESS
0x0000FFFF
0x0001FFFF
0x0002FFFF
0x0003BFFF
0x0003FFFF
0x0004FFFF
0x0005FFFF
0x0006FFFF
0x0007FFFF
0x00003FFF
0x00007FFF
0x00017FFF
0x00027FFF
0x00037FFF
MEMORY ARRAYS
(OR BANKS)
(256K Bytes)
(256K Bytes)
BANK0
BANK1
www.ti.com