TMS470R1B512 AD [Analog Devices], TMS470R1B512 Datasheet - Page 36

• Manufacturer Part Number: TMS470R1B512
• Description: 16/32-Bit RISC Flash Microcontroller
• Manufacturer: AD [Analog Devices]

TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
36
SPIn SLAVE MODE TIMING PARAMETERS
SPIn Slave Mode External Timing Parameters
(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)
(1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
(2) If the SPI is in slave mode, the following must be true: t
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4) t
(5) When the SPIn is in slave mode, the following must be true:
(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
NO.
2
3
4
5
6
7
1
(6)
(6)
(6)
(6)
(6)
(6)
For PS values from 1 to 255: t
For PS values of 0: t
c(ICLK)
t
t
t
t
t
t
SOMI)S
t
SOMI)S
t
SOMI)S
t
SOMI)S
t
SPCL)S
t
SPCH)S
t
SIMO)S
t
SIMO)S
c(SPC)S
w(SPCH)S
w(SPCL)S
w(SPCL)S
w(SPCH)S
d(SPCH-
d(SPCL-
v(SPCH-
v(SPCL-
su(SIMO-
su(SIMO-
v(SPCL-
v(SPCH-
(clock polarity = 0)
(clock polarity = 1)
= interface clock cycle time = 1/f
SPInSOMI
SPInSIMO
Cycle time, SPInCLK
Pulse duration, SPInCLK high (clock polarity = 0)
Pulse duration, SPInCLK low (clock polarity = 1)
Pulse duration, SPInCLK low (clock polarity = 0)
Pulse duration, SPInCLK high (clock polarity = 1)
Delay time, SPInCLK high to SPInSOMI valid
(clock polarity = 0)
Delay time, SPInCLK low to SPInSOMI valid
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
Valid time, SPInSOMI data valid after SPInCLK low (clock
polarity = 1)
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 0)
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK low (clock
polarity = 0)
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
SPInCLK
SPInCLK
c(SPC)S
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
= 2t
c(SPC)S
c(ICLK)
(5)
(ICLK)
(PS +1)t
100 ns.
c(ICLK)
Submit Documentation Feedback
4
2
c(SPC)S
100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
(PS + 1) t
1
5
5
6
c(ICLK)
3
7
0.5t
0.5t
0.5t
0.5t
, where PS = prescale value set in SPInCTL1[12:5].
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
t
t
c(SPC)S
c(SPC)S
MIN
100
– 0.25t
– 0.25t
– 0.25t
– 0.25t
6
6
6
6
– 6 – t
– 6 – t
(1) (2) (3) (4)
c(ICLK)
c(ICLK)
c(ICLK)
c(ICLK)
r
f
(see
0.5t
0.5t
0.5t
0.5t
Figure
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
256t
6 + t
14)
MAX
6 + t
+ 0.25t
+ 0.25t
+ 0.25t
+ 0.25t
c(ICLK)
r
f
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c(ICLK)
c(ICLK)
c(ICLK)
c(ICLK)
UNIT
ns
ns
ns
ns
ns
ns
ns