LM3S1911-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S1911-IQC20-A0 Datasheet - Page 86
![no-image](/images/no-image-200.jpg)
LM3S1911-IQC20-A0
Manufacturer Part Number
LM3S1911-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S1911-IQC20-A0.pdf
(426 pages)
- Current page: 86 of 426
- Download datasheet (5Mb)
System Control
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x0000.C0FF
86
Reset
Reset
Type
Type
Bit/Field
31:16
13:8
15
14
7
6
5
4
3
2
CCP7
RO
RO
31
15
0
1
Register 17: Device Capabilities 4 (DC4), offset 0x01C
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Ethernet MAC
and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2,
and DCGC2 clock control registers and the SRCR2 software reset control register.
CCP6
RO
RO
30
14
0
1
reserved
reserved
GPIOG
GPIOH
GPIOF
GPIOE
GPIOD
GPIOC
Name
CCP7
CCP6
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
reserved
RO
RO
26
10
0
0
Reset
0
1
1
0
1
1
1
1
1
1
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CCP7 Pin Present
When set, indicates that Capture/Compare/PWM pin 7 is present.
CCP6 Pin Present
When set, indicates that Capture/Compare/PWM pin 6 is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Port H Present
When set, indicates that GPIO Port H is present.
GPIO Port G Present
When set, indicates that GPIO Port G is present.
GPIO Port F Present
When set, indicates that GPIO Port F is present.
GPIO Port E Present
When set, indicates that GPIO Port E is present.
GPIO Port D Present
When set, indicates that GPIO Port D is present.
GPIO Port C Present
When set, indicates that GPIO Port C is present.
RO
RO
24
0
8
0
reserved
GPIOH
RO
RO
23
0
7
1
GPIOG
RO
RO
22
0
6
1
GPIOF
RO
RO
21
0
5
1
GPIOE
RO
RO
20
0
4
1
GPIOD
RO
RO
19
0
3
1
GPIOC
RO
RO
18
0
2
1
October 09, 2007
GPIOB
RO
RO
17
0
1
1
GPIOA
RO
RO
16
0
0
1
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