LM3S1911-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S1911-IQC20-A0 Datasheet - Page 206
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LM3S1911-IQC20-A0
Manufacturer Part Number
LM3S1911-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S1911-IQC20-A0.pdf
(426 pages)
- Current page: 206 of 426
- Download datasheet (5Mb)
General-Purpose Timers
GPTM TimerA Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x004
Type R/W, reset 0x0000.0000
206
Reset
Reset
Type
Type
Bit/Field
31:4
3
2
RO
RO
31
15
0
0
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
RO
RO
30
14
0
0
reserved
TACMR
TAAMS
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
0
0
RO
RO
RO
26
10
0
0
reserved
Reset
0x00
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM TimerA Alternate Mode Select
The TAAMS values are defined as follows:
GPTM TimerA Capture Mode
The TACMR values are defined as follows:
RO
RO
Value
Value
24
0
8
0
reserved
0
1
0
1
Description
Capture mode is enabled.
PWM mode is enabled.
Note:
Description
Edge-Count mode.
Edge-Time mode.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
RO
RO
21
0
5
0
RO
RO
20
0
4
0
TAAMS
R/W
RO
19
0
3
0
TACMR
R/W
RO
18
0
2
0
October 09, 2007
R/W
RO
17
0
1
0
TAMR
R/W
RO
16
0
0
0
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