MC9S12DJ256 MOTOROLA [Motorola, Inc], MC9S12DJ256 Datasheet - Page 58
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MC9S12DJ256
Manufacturer Part Number
MC9S12DJ256
Description
MC9S12DT256 Device User Guide V03.03
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC9S12DJ256.pdf
(130 pages)
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Pin Name
Funct. 1
PT[7:0]
PP4
PP3
PP2
PP1
PP0
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
MC9S12DT256 Device User Guide — V03.03
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
56
Pin Name
Funct. 2
IOC[7:0]
MOSI0
MISO0
KWP4
KWP3
KWP2
KWP1
KWP0
SCK0
RXD1
RXD0
TXD1
TXD0
SS0
Pin Name
Funct. 3
PWM4
PWM3
PWM2
PWM1
PWM0
—
—
—
—
—
—
—
—
—
Pin Name
Funct. 4
MISO2
MOSI1
MISO1
SCK1
SS1
—
—
—
—
—
—
—
—
—
Pin Name
Funct. 5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Supply
Power
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
PERP/
PERP/
PERP/
PERP/
PERP/
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERT/
PERS/
CTRL
PPSP
PPSP
PPSP
PPSP
PPSP
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPST
Internal Pull
Resistor
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Reset
State
Up
Up
Up
Up
Up
Up
Up
Up
Port P I/O, Interrupt, Channel 4 of
PWM, MISO2 of SPI2
Port P I/O, Interrupt, Channel 3 of
PWM, SS of SPI1
Port P I/O, Interrupt, Channel 2 of
PWM, SCK of SPI1
Port P I/O, Interrupt, Channel 1 of
PWM, MOSI of SPI1
Port P I/O, Interrupt, Channel 0 of
PWM, MISO2 of SPI1
Port S I/O, SS of SPI0
Port S I/O, SCK of SPI0
Port S I/O, MOSI of SPI0
Port S I/O, MISO of SPI0
Port S I/O, TXD of SCI1
Port S I/O, RXD of SCI1
Port S I/O, TXD of SCI0
Port S I/O, RXD of SCI0
Port T I/O, Timer channels
Description