MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 340

• Manufacturer Part Number: MC9S12Q
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
10.4.7.1
The MSCAN supports four interrupt vectors (see
(for details see sections from
(CANRIER),” to
10.4.7.2
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXEx flag of the empty message buffer is set.
10.4.7.3
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO.
This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are
multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the
foreground buffer.
10.4.7.4
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCN internal sleep mode.
WUPE (see
10.4.7.5
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition
occurrs.
conditions:
340
•
•
Overrun — An overrun condition of the receiver FIFO as described in
Structures,” occurred.
CAN Status Change — The actual value of the transmit and receive error counters control the
CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx-
warning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change, which
caused the error condition, is indicated by the TSTAT and RSTAT flags (see
Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)
Section 10.3.2.1, “MSCAN Control Register 0
Wake-Up Interrupt (WUPIF)
Error Interrupts Interrupt (CSCIF, OVRIF)
Receive Interrupt (RXF)
Transmit Interrupts (TXE[2:0])
Description of Interrupt Operation
Transmit Interrupt
Receive Interrupt
Wake-Up Interrupt
Error Interrupt
The dedicated interrupt vector addresses are defined in the
Interrupts
Section 10.3.2.8, “MSCAN Transmitter Interrupt Enable Register
Interrupt Source
chapter.
Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register
Table 10-36. Interrupt Vectors
MC9S12Q128
Rev 1.09
NOTE
Table
CCR Mask
10-36), any of which can be individually masked
I bit
I bit
I bit
I bit
(CANCTL0)”) must be enabled.
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CANTIER (TXEIE[2:0])
Local Enable
Resets and
indicates one of the following
Section 10.4.2.3, “Receive
(CANTIER)”).
Section 10.3.2.5,
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