MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 311
MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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Module Base + 0x0018 (CANIDAR4)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
AC[7:0]
Figure 10-20. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Field
7:0
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
0x0019 (CANIDAR5)
0x001A (CANIDAR6)
0x001B (CANIDAR7)
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
AC7
AC7
AC7
AC7
0
0
0
0
7
7
7
7
Table 10-20. CANIDAR4–CANIDAR7 Register Field Descriptions
AC6
AC6
AC6
AC6
6
0
6
0
6
0
6
0
AC5
AC5
AC5
AC5
0
0
0
0
5
5
5
5
MC9S12Q128
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
Rev 1.09
AC4
AC4
AC4
AC4
4
0
4
0
4
0
4
0
Description
AC3
AC3
AC3
AC3
0
0
0
0
3
3
3
3
AC2
AC2
AC2
AC2
2
0
2
0
2
0
2
0
AC1
AC1
AC1
AC1
0
0
0
0
1
1
1
1
AC0
AC0
AC0
AC0
0
0
0
0
0
0
0
0
311
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