MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 224
MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
8.1.2.2
8.1.3
Figure 8-1
224
•
•
•
Stop Mode
Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power
standby mode. This aborts any conversion sequence in progress. During recovery from stop mode,
there must be a minimum delay for the stop recovery time, t
conversion sequence.
Wait Mode
Entering wait mode the ATD conversion either continues or aborts for low power depending on the
logical value of the AWAIT bit.
Freeze Mode
In freeze mode the ATD10B8C will behave according to the logical values of the FRZ1 and FRZ0
bits. This is useful for debugging and emulation.
is a block diagram of the ATD.
Block Diagram
MCU Operating Modes
COMPLETE INTERRUPT
CONVERSION
BUS CLOCK
AN7 / PAD7
AN6 / PAD6
AN5 / PAD5
AN4 / PAD4
AN3 / PAD3
AN2 / PAD2
AN1 / PAD1
AN0 / PAD0
V
V
V
V
DDA
SSA
RH
RL
Figure 8-1. ATD10B8C Block Diagram
ATD10B8C
ANALOG
PRESCALER
MUX
CLOCK
APPROXIMATION
REGISTER (SAR)
MC9S12Q128
SUCCESSIVE
AND DAC
Rev 1.09
ATD INPUT ENABLE REGISTER
MODE AND TIMING CONTROL
1
ATD CLOCK
SAMPLE & HOLD
PORT AD DATA REGISTER
SR
RESULTS
, before initiating a new ATD
1
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
ATD 6
ATD 7
COMPARATOR
+
–
Freescale Semiconductor
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