MCF51JU128VHS FREESCALE [Freescale Semiconductor, Inc], MCF51JU128VHS Datasheet - Page 50

• Manufacturer Part Number: MCF51JU128VHS
• Description: MCF51JU128
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Communication interfaces
6.8.5 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
All timing shown is also with respect to input signal transitions of 3 ns and a 50 pF
maximum load.
1. This parameter is limited in VLPx modes.
2. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
50
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
Num.
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_TX_BCLK cycle time (output)
I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid
MCF51JU128 Advance Information Data Sheet, Rev. 1, 08/2011.
Characteristic
Table 36. I2S/SAI master mode timing
1
1
1
Preliminary
2
1.71
40
45%
80
160
45%
—
0
—
0
25
0
—
Min.
3.6
55%
—
—
55%
15
—
15
—
—
—
21
Max.
Freescale Semiconductor, Inc.
V
ns
MCLK period
ns
BCLK period
ns
ns
ns
ns
ns
ns
ns
Unit