MCF51JU128VHS FREESCALE [Freescale Semiconductor, Inc], MCF51JU128VHS Datasheet - Page 23

• Manufacturer Part Number: MCF51JU128VHS
• Description: MCF51JU128
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1. The startup time is defined as the time between the IRC being enabled, either by the MCG or by the IRCLKEN bit being
2. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification was obtained at TBD frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
9. Excludes any oscillator currents that are also consuming power while PLL is in operation.
10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Freescale Semiconductor, Inc.
Symbol
Symbol
I
t
DDOSC
pll_lock
set, and the first edge of the internal reference clock.
mode).
(Δf
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
D
D
each PCB and results will vary.
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
V
lock
DD
unl
dco_t
) over voltage and temperature should be considered.
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
Supply voltage
Supply current — low-power mode (HGO=0)
Description
Description
• 32 kHz
• 1 MHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
MCF51JU128 Advance Information Data Sheet, Rev. 1, 08/2011.
Table 15. Oscillator DC electrical specifications
Table 14. MCG specifications (continued)
Table continues on the next page...
Preliminary
± 1.49
± 4.47
1.71
Min.
Min.
—
—
—
—
—
—
—
—
Typ.
Typ.
500
200
200
300
950
1.2
1.5
—
—
—
—
150 × 10
+ 1075(1/
± 2.98
± 5.97
f
Max.
pll_ref
Max.
3.6
—
—
—
—
—
—
—
)
-6
Unit
Unit
mA
mA
μA
μA
μA
μA
nA
%
%
V
s
Clock modules
Notes
Notes
11
1
23