MCF51JU128VHS FREESCALE [Freescale Semiconductor, Inc], MCF51JU128VHS Datasheet - Page 31

• Manufacturer Part Number: MCF51JU128VHS
• Description: MCF51JU128
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

6.4.3 Mini-Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Mini-Flexbus output clock (FB_CLK). All other timing relationships
can be derived from these values.
Freescale Semiconductor, Inc.
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Num
FB1
Num
EP6
EP7
EP8
EP9
Operating voltage
Frequency of operation
Clock period
Description
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Description
Table 21. EzPort switching specifications (continued)
MCF51JU128 Advance Information Data Sheet, Rev. 1, 08/2011.
Table 22. Flexbus switching specifications
EP3
EP5
Figure 6. EzPort Timing Diagram
Table continues on the next page...
EP6
EP4
EP7
Preliminary
EP8
EP9
Min.
EP2
2.7
20
—
Min.
0.0
0.0
—
—
Max.
3.6
25
—
Memories and memory interfaces
Max.
25
12
—
—
MHz
Unit
ns
V
Unit
Notes
ns
ns
ns
ns
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