MC908JL16CFAE FREESCALE [Freescale Semiconductor, Inc], MC908JL16CFAE Datasheet - Page 47

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MC908JL16CFAE

Manufacturer Part Number
MC908JL16CFAE
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
4.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, OSCOUT, as shown in
4.2.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency divided by four.
4.2.2 Clock Start-Up from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 ICLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks
start upon completion of the timeout.
Freescale Semiconductor
$FE03
$FE04
$FE05
$FE06
Addr.
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Status Register 3
Register Name
Break Flag Control
Register (BFCR)
XTALCLK / RCCLK
INTERNAL RC
OSCILLATOR
(INT1)
(INT2)
(INT3)
Figure 4-2. SIM I/O Register Summary (Continued)
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
BCFE
Bit 7
MC68HC908JL16 Data Sheet, Rev. 1.1
IF14
IF6
Figure 4-3. SIM Clock Signals
R
R
R
0
0
0
0
0
OSC
÷
2
= Unimplemented
IF13
IF5
R
R
R
R
6
0
0
0
0
OSCOUT
ICLK
IF12
IF4
R
R
R
R
5
0
0
0
0
IF11
IF3
R
R
R
R
4
0
0
0
0
÷
SIM COUNTER
2
SIM
SIM Bus Clock Control and Generation
IF10
R
R
R
R
R
3
0
0
0
0
0
GENERATORS
BUS CLOCK
Figure
= Reserved
IF1
R
R
R
R
2
0
0
0
0
0
4-3.
IF8
R
R
R
R
1
0
0
0
0
0
Bit 0
IF15
IF7
R
R
R
R
0
0
0
0
47

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