MC908JL16CFAE FREESCALE [Freescale Semiconductor, Inc], MC908JL16CFAE Datasheet - Page 120

• Manufacturer Part Number: MC908JL16CFAE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Multi-Master IIC Interface (MMIIC)
transferred to the output circuit until the next calling from a master. The transmit buffer empty flag remains
cleared (MMTXBE = 0).
In master mode, the data in MMDTR will be transferred to the output circuit when:
If the slave does not return an acknowledge bit (MMRXAK = 1), the master will generate a "stop" or
"repeated start" condition. The data in the MMDTR will not be transferred to the output circuit. The
transmit buffer empty flag remains cleared (MMTXBE = 0).
The sequence of events for slave transmit and master transmit are illustrated in
8.8.6 Multi-Master IIC Data Receive Register (MMDRR)
When the MMIIC module is enabled, MMEN = 1, data in this read-only register depends on whether
module is in master or slave mode.
In slave mode, the data in MMDRR is:
In master mode, the data in the MMDRR is:
When the MMDRR is read by the CPU, the receive buffer full flag is cleared (MMRXBF = 0), and the next
received data is loaded to the MMDRR. Each time when new data is loaded to the MMDRR, the MMRXIF
interrupt flag is set, indicating that new data is available in MMDRR.
The sequence of events for slave receive and master receive are illustrated in
8.9 Programming Considerations
When the MMIIC module detects an arbitration loss in master mode, it will release both SDA and SCL
lines immediately. But if there are no further STOP conditions detected, the module will hang up.
Therefore, it is recommended to have time-out software to recover from such ill condition. The software
can start the time-out counter by looking at the MMBB (Bus Busy) flag in the MIMCR and reset the counter
on the completion of one byte transmission. If a time-out occur, software can clear the MMEN bit (disable
MMIIC module) to release the bus, and hence clearing the MMBB flag. This is the only way to clear the
MMBB flag by software if the module hangs up due to a no STOP condition received. The MMIIC can
resume operation again by setting the MMEN bit.
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the module receives an acknowledge bit (MMRXAK = 0), after
setting master transmit mode (MMRW = 0), and the calling address has been transmitted; or
the previous data in the output circuit has be transmitted and the receiving slave returns an
acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0).
the calling address from the master when the address match flag is set (MMATCH = 1); or
the last data received when MMATCH = 0.
the last data received.
Address: $0045
Reset:
Read: MMRD7
Write:
Figure 8-9. Multi-Master IIC Data Receive Register (MMDRR)
Bit 7
0
= Unimplemented
MMRD6
6
0
MC68HC908JL16 Data Sheet, Rev. 1.1
MMRD5
5
0
MMRD4
4
0
MMRD3
3
0
MMRD2
2
0
MMRD1
1
0
Figure
Figure
Freescale Semiconductor
MMRD0
8-10.
Bit 0
8-10.
0