DSPIC30F5011 MICROCHIP [Microchip Technology], DSPIC30F5011 Datasheet - Page 83

• Manufacturer Part Number: DSPIC30F5011
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

13.0
This section describes the output compare module and
associated Operational modes. The features provided
by this module are useful in applications requiring
Operational modes, such as:
• Generation of Variable Width Output Pulses
• Power Factor Correction
Figure 13-1 depicts a block diagram of the output
compare module.
The key operational features of the output compare
module include:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare During Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
FIGURE 13-1:
 2004 Microchip Technology Inc.
Note:
OUTPUT COMPARE MODULE
From GP
Timer Module
TMR2<15:0
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
0
OUTPUT COMPARE MODE BLOCK DIAGRAM
Comparator
OCxRS
OCxR
TMR3<15:0>
1
OCTSEL
T2P2_MATCH
Preliminary
0
These Operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where
x = 1,2,3,...,N). The dsPIC devices contain up to 8
compare channels (i.e., the maximum value of N is 8).
OCxRS and OCxR in Figure 13-1 represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
T3P3_MATCH
Mode Select
OCM<2:0>
dsPIC30F5011/5013
1
Output
3
Logic
Set Flag bit
OCxIF
R
S
Q
Output
Enable
(for x = 1, 2, 3 or 4)
(for x = 5, 6, 7 or 8)
or OCFB
OCFA
DS70116C-page 81
OCx